Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10023207 | Zip line apparatus | — | 2018-07-17 |
| 9754065 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Terry Borer, Gabriel Quan, Deshanand Singh, Chris G. Sanford, Vaughn Betz +2 more | 2017-09-05 |
| 9589090 | Method and apparatus for performing multiple stage physical synthesis | Deshanand Singh, Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno | 2017-03-07 |
| 9122826 | Method and apparatus for performing compilation using multiple design flows | Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan | 2015-09-01 |
| 8985027 | Zip line apparatus | — | 2015-03-24 |
| 8856702 | Method and apparatus for performing multiple stage physical synthesis | Deshanand Singh, Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno | 2014-10-07 |
| 8589838 | M/A for performing incremental compilation using top-down and bottom-up design approaches | Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan | 2013-11-19 |
| 8589849 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Terry Borer, Gabriel Quan, Deshanand Singh, Chris G. Sanford, Vaughn Betz +2 more | 2013-11-19 |
| 8510688 | Method and apparatus for performing multiple stage physical synthesis | Deshanand Singh, Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno | 2013-08-13 |
| 8296696 | Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis | Gordon Raymond Chiu, Deshanand Singh, Valavan Manohararajah, Ivan Blunno | 2012-10-23 |
| 8250505 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches | Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan | 2012-08-21 |
| 8095914 | Methods for instruction trace decomposition | Deshanand Singh | 2012-01-10 |
| 7996797 | Method and apparatus for performing multiple stage physical synthesis | Deshanand Singh, Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno | 2011-08-09 |
| 7797666 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories | Gordon Raymond Chiu, Deshanand Singh, Valavan Manohararajah | 2010-09-14 |
| 7669157 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches | Terry Borer, Andrew Leaver, David Karchmer, Gabriel Quan | 2010-02-23 |
| 7620925 | Method and apparatus for performing post-placement routability optimization | Valavan Manohararajah, Gordon Raymond Chiu, Deshanand Singh | 2009-11-17 |
| 7594204 | Method and apparatus for performing layout-driven optimizations on field programmable gate arrays | Deshanand Singh, Paul McHardy, Chris G. Sanford, Gabriel Quan, Terry Borer +3 more | 2009-09-22 |
| 7594208 | Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage | Terry Borer, Ian Chesal, James Schleicher, David W. Mendel, Mike Hutton +7 more | 2009-09-22 |
| 7509597 | Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams | Valavan Manohararajah, Deshanand Singh | 2009-03-24 |
| 7500216 | Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines | Ivan Blunno, Gordon Raymond Chiu, Deshanand Singh, Valavan Manohararajah | 2009-03-03 |
| 7464362 | Method and apparatus for performing incremental compilation | Terry Borer, David Karchmer, Jason Govig, Andrew Leaver, Gabriel Quan +2 more | 2008-12-09 |
| 7444613 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories | Gordon Raymond Chiu, Deshanand Singh, Valavan Manohararajah | 2008-10-28 |
| 7412677 | Detecting reducible registers | Valavan Manohararajah, Gordon Raymond Chiu, Deshanand Singh | 2008-08-12 |
| 7401314 | Method and apparatus for performing compound duplication of components on field programmable gate arrays | Karl Schabas, Deshanand Singh, Terry Borer, Shawn Malhotra | 2008-07-15 |
| 7389489 | Techniques for editing circuit design files to be compatible with a new programmable IC | Ian Chesal, Kevin Chan, Subianto Windoro, Minh V. Mac, Terry Borer +2 more | 2008-06-17 |