Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336288 | Array of vertical transistors and method used in forming an array of vertical transistors | Yi Fang Lee, Jaydip Guha, Lars Heineck, Kamal M. Karda, Si-Woo Lee +3 more | 2025-06-17 |
| 11903183 | Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices | Byung Yoon Kim, Si-Woo Lee, Mark A. Zaleski | 2024-02-13 |
| 11848282 | Semiconductor devices having crack-inhibiting structures | Hyunsuk Chun, Shams U. Arifeen | 2023-12-19 |
| 11616028 | Semiconductor devices having crack-inhibiting structures | Shams U. Arifeen, Hyunsuk Chun, Keizo Kawakita | 2023-03-28 |
| 11488981 | Array of vertical transistors and method used in forming an array of vertical transistors | Yi Fang Lee, Jaydip Guha, Lars Heineck, Kamal M. Karda, Si-Woo Lee +3 more | 2022-11-01 |
| 11444037 | Semiconductor devices having crack-inhibiting structures | Hyunsuk Chun, Shams U. Arifeen | 2022-09-13 |
| 10891410 | User-defined rule engine | Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Guo-Ting Wang | 2021-01-12 |
| 10854514 | Microelectronic devices including two contacts | Tieh-Chiang Wu, Wen-Chieh Wang | 2020-12-01 |
| 10811365 | Semiconductor devices having crack-inhibiting structures | Shams U. Arifeen, Hyunsuk Chun, Keizo Kawakita | 2020-10-20 |
| 10784212 | Semiconductor devices having crack-inhibiting structures | Hyunsuk Chun, Shams U. Arifeen | 2020-09-22 |
| 10388564 | Method for fabricating a memory device having two contacts | Tieh-Chiang Wu, Wen-Chieh Wang | 2019-08-20 |
| 9419001 | Method for forming cell contact | Tieh-Chiang Wu, Wen-Chieh Wang | 2016-08-16 |
| 9117759 | Methods of forming bulb-shaped trenches in silicon | Sanjeev Sapra, Cheng Chen, Hung-Ming Tsai | 2015-08-25 |
| 9041099 | Single-sided access device and fabrication method thereof | Shyam Surthi | 2015-05-26 |
| 9012303 | Method for fabricating semiconductor device with vertical transistor structure | Ying-Cheng Chuang, Shyam Surthi | 2015-04-21 |
| 8901631 | Vertical transistor in semiconductor device and method for fabricating the same | Ying-Cheng Chuang, Shyam Surthi | 2014-12-02 |
| 8658538 | Method of fabricating memory device | Ying-Cheng Chuang, Ping Hsu, Ming-Cheng Chang, Hung-Ming Tsai | 2014-02-25 |
| 8647988 | Memory device and method of fabricating the same | Ying-Cheng Chuang, Ping Hsu, Ming-Cheng Chang, Hung-Ming Tsai | 2014-02-11 |
| 8426925 | Memory device and method of fabricating the same | Ying-Cheng Chuang, Ping Hsu, Ming-Cheng Chang, Hung-Ming Tsai | 2013-04-23 |
| 8415728 | Memory device and method of fabricating the same | Ying-Cheng Chuang, Ping Hsu, Ming-Cheng Chang, Hung-Ming Tsai | 2013-04-09 |
| 8334196 | Methods of forming conductive contacts in the fabrication of integrated circuitry | Ying-Cheng Chuang, Hung-Ming Tsai, Ping Hsu, Ming-Cheng Chang | 2012-12-18 |
| 7074700 | Method for isolation layer for a vertical DRAM | Cheng-Chih Huang, Chen-Chou Huang, Sheng-Tsung Chen | 2006-07-11 |
| 6962847 | Method for forming a self-aligned buried strap in a vertical memory cell | Cheng-Chih Huang, Neng-Tai Shih, Chen-Chou Huang | 2005-11-08 |
| 6958283 | Method for fabricating trench isolation | Chien-Mao Liao, Tzu-En Ho, Chang-Rong Wu, Chih-How Chang, Sheng-Tsung Chen +3 more | 2005-10-25 |
| 6946359 | Method for fabricating trench isolations with high aspect ratio | Neng-Tai Shih, Wen-Sheng Liao, Chih-How Chang | 2005-09-20 |