Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8522096 | Method and apparatus for testing 3D integrated circuits | Laung-Terng Wang, Nur A. Touba, Michael Hsiao, Zhigang Jiang | 2013-08-27 |
| 8458544 | Multiple-capture DFT system to reduce peak capture power during self-test or scan test | Laung-Terng Wang, Hao-Jan Chao | 2013-06-04 |
| 8418100 | Robust scan synthesis for protecting soft errors | Laung-Terng Wang, Nur A. Touba, Ravi Apte | 2013-04-09 |
| 8335954 | Method and apparatus for low-pin-count scan compression | Nur A. Touba, Laung-Terng Wang | 2012-12-18 |
| 8230282 | Method and apparatus for low-pin-count scan compression | Nur A. Touba, Laung-Terng Wang, Zhigang Jiang, Jianping Yan | 2012-07-24 |
| 8161441 | Robust scan synthesis for protecting soft errors | Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Ravi Apte | 2012-04-17 |
| 8091002 | Multiple-capture DFT system to reduce peak capture power during self-test or scan test | Laung-Terng Wang, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu +3 more | 2012-01-03 |
| 7996741 | Method and apparatus for low-pin-count scan compression | Nur A. Touba, Laung-Terng Wang, Zhigang Jiang, Jianping Yan | 2011-08-09 |
| 7945833 | Method and apparatus for pipelined scan compression | Laung-Terng Wang, Nur A. Touba, Boryau (Jack) Sheu, Zhigang Jiang | 2011-05-17 |
| 7783940 | Apparatus for redundancy reconfiguration of faculty memories | Lizhen Yu, Zhigang Jiang, Laung-Terng Wang | 2010-08-24 |
| 7779322 | Compacting test responses using X-driven compactor | Zhigang Wang, Laung-Terng Wang, Xiaoqing Wen, Boryau (Jack) Sheu, Zhigang Jiang | 2010-08-17 |
| 7721172 | Method and apparatus for broadcasting test patterns in a scan-based integrated circuit | Laung-Terng Wang, Boryau (Jack) Sheu, Zhigang Jiang, Zhigang Wang | 2010-05-18 |
| 7590905 | Method and apparatus for pipelined scan compression | Khader S. Abdel-Hafez, Laung-Terng Wang, Boryau (Jack) Sheu | 2009-09-15 |
| 7512851 | Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit | Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Fei-Sheng Hsu +4 more | 2009-03-31 |
| 7412637 | Method and apparatus for broadcasting test patterns in a scan based integrated circuit | Laung-Terng Wang, Boryau (Jack) Sheu, Zhigang Jiang, Zhigang Wang | 2008-08-12 |
| 7231570 | Method and apparatus for multi-level scan compression | Laung-Terng Wang, Khader S. Abdel-Hafez, Boryau (Jack) Sheu | 2007-06-12 |
| 6052808 | Maintenance registers with Boundary Scan interface | Ramesh Karri, Charles E. Stroud | 2000-04-18 |
| 5332996 | Method and apparatus for all code testing | Miroslaw Guzinski, James L. Lewandowski, Victor J. Velasco | 1994-07-26 |