SL

Shih-Hsien Lo

IBM: 12 patents #9,222 of 70,183Top 15%
Overall (All Time): #417,225 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10083880 Hybrid ETSOI structure to minimize noise coupling from TSV Chung-Hsun Lin, Yu-Shiang Lin, Joel A. Silberman 2018-09-25
9653615 Hybrid ETSOI structure to minimize noise coupling from TSV Chung-Hsun Lin, Yu-Shiang Lin, Joel A. Silberman 2017-05-16
9087909 Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSV Chung-Hsun Lin, Yu-Shiang Lin, Joel A. Silberman 2015-07-21
8835191 Nanowire stress sensors and stress sensor integrated circuits, design structures for a stress sensor integrated circuit, and related methods Andres Bryant, Oki Gunawan, Jeffrey W. Sleight 2014-09-16
8835997 Low extension dose implants in SRAM fabrication Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight 2014-09-16
8822295 Low extension dose implants in SRAM fabrication Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight 2014-09-02
8614492 Nanowire stress sensors, stress sensor integrated circuits, and design structures for a stress sensor integrated circuit Andres Bryant, Oki Gunawan, Jeffrey W. Sleight 2013-12-24
8526219 Enhanced static random access memory stability using asymmetric access transistors and design structure for same Aditya Bansal, Ching-Te Chuang, Jae-Joon Kim, Rahul M. Rao 2013-09-03
8381156 3D inter-stratum connectivity robustness Michael P. Beakes, Michael R. Scheuermann, Matthew R. Wordeman 2013-02-19
8139400 Enhanced static random access memory stability using asymmetric access transistors and design structure for same Aditya Bansal, Ching-Te Chuang, Jae-Joon Kim, Rahul M. Rao 2012-03-20
7342287 Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures Ching-Te Chuang, Koushik K. Das, Jeffrey W. Sleight 2008-03-11
7274217 High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs Ching-Te Chuang, Koushik K. Das 2007-09-25