Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12002846 | Integrated circuits having dielectric layers including an anti-reflective coating | Poornika Fernandes, David M. Curran, Stephen Arlon Meisner, Bhaskar Srinivasan, Guruvayurappan Mathur +3 more | 2024-06-04 |
| 11605587 | Methods for etching metal interconnect layers | Poornika Fernandes, Bhaskar Srinivasan, Guruvayurappan Mathur | 2023-03-14 |
| 11522043 | IC with matched thin film resistors | Tae Seung Kim, Steven Lee Prins, Can Duan, Abbas Ali, Erich Wesley Kinder | 2022-12-06 |
| 11171200 | Integrated circuits having dielectric layers including an anti-reflective coating | Poornika Fernandes, David M. Curran, Stephen Arion Meisner, Bhaskar Srinivasan, Guruvayurappan Mathur +3 more | 2021-11-09 |
| 10756095 | SRAM cell with T-shaped contact | Theodore W. Houston, Thomas J. Aton | 2020-08-25 |
| 10748913 | SRAM cell with T-shaped contact | Theodore W. Houston, Thomas J. Aton | 2020-08-18 |
| 10566200 | Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings | Abbas Ali, Binghua Hu, Stephanie L. Hilbun, Ronald Chin, Jarvis Benjamin Jacobs | 2020-02-18 |
| 10199380 | SRAM cell with T-shaped contact | Theodore W. Houston, Thomas J. Aton | 2019-02-05 |
| 10163911 | SRAM cell with T-shaped contact | Theodore W. Houston, Thomas J. Aton | 2018-12-25 |
| 10103171 | Metal on elongated contacts | James Walter Blatchford | 2018-10-16 |
| 10043714 | Elongated contacts using litho-freeze-litho-etch process | James Walter Blatchford | 2018-08-07 |
| 9620419 | Elongated contacts using litho-freeze-litho-etch process | James Walter Blatchford | 2017-04-11 |
| 9343332 | Alignment to multiple layers | Thomas J. Aton, Steven Lee Prins | 2016-05-17 |
| 9312170 | Metal on elongated contacts | James Walter Blatchford | 2016-04-12 |
| 9305848 | Elongated contacts using litho-freeze-litho-etch process | James Walter Blatchford | 2016-04-05 |
| 9117775 | Alignment to multiple layers | Thomas J. Aton, Steven Lee Prins | 2015-08-25 |
| 9054214 | Methodology of forming CMOS gates on the secondary axis using double-patterning technique | Gregory Charles Baldwin | 2015-06-09 |
| 9024450 | Two-track cross-connect in double-patterned structure using rectangular via | James Walter Blatchford | 2015-05-05 |
| 8580675 | Two-track cross-connect in double-patterned structure using rectangular via | James Walter Blatchford | 2013-11-12 |
| 7987436 | Sub-resolution assist feature to improve symmetry for contact hole lithography | Mark Terry, Robert Soper | 2011-07-26 |
| 7745067 | Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements | James Walter Blatchford | 2010-06-29 |
| 7512928 | Sub-resolution assist feature to improve symmetry for contact hole lithography | Mark Terry, Robert Soper | 2009-03-31 |
| 7461367 | Modifying merged sub-resolution assist features of a photolithographic mask | Sean O'Brien | 2008-12-02 |
| 7425502 | Minimizing resist poisoning in the manufacture of semiconductor devices | Zhijian Lu, Thomas Wolf | 2008-09-16 |
| 7262129 | Minimizing resist poisoning in the manufacture of semiconductor devices | Zhijian Lu, Thomas Wolf | 2007-08-28 |