Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651232 | Method and system for progressive clock tree or mesh construction concurrently with physical design | Lawrence Pileggi, Christopher Dunn, Majid Sarrafzadeh, Tong Gao, Salil Ravindra Raje | 2003-11-18 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Lawrence Pileggi, Sharad Malik, Emre Tuncer, Abhijeet Chakraborty, Altan Odabasioglu +1 more | 2002-04-02 |
| 6074429 | Optimizing combinational circuit layout through iterative restructuring | Stephen C. Moore, David Theodore Blaauw, Rajendran Panda, Gopalakrishnan Vijayan | 2000-06-13 |
| 5903471 | Method for optimizing element sizes in a semiconductor device | Timothy J. Edwards, Joseph W. Norton, Abhijit Dharchoudhury, David Theodore Blaauw | 1999-05-11 |
| 5790415 | Complementary network reduction for load modeling | Abhijit Dharchoudhury, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton | 1998-08-04 |
| 5787008 | Simulation corrected sensitivity | Abhijit Dharchoudhury, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton, Peter R. O'Brien | 1998-07-28 |
| 5751593 | Accurate delay prediction based on multi-model analysis | Abhijit Dharchoudhury, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton | 1998-05-12 |