Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7356674 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine | Anuj Dua, James E. McCormick, Jr., Stephen R. Undy, Barry J. Arnold, David Carl Kubicek +1 more | 2008-04-08 |
| 7343479 | Method and apparatus for implementing two architectures in a chip | Patrick Knebel, Kevin Safford, Donald Soltis, Joel D. Lamb, Stephen R. Undy | 2008-03-11 |
| 7139936 | Method and apparatus for verifying the correctness of a processor behavioral model | Jeremy Petsinger, Kevin Safford, Karl Brummel, Bruce Long, Patrick Knebel | 2006-11-21 |
| 6789186 | Method and apparatus to reduce penalty of microcode lookup | Kevin Safford, Jane Wang, Chris Poirier | 2004-09-07 |
| 6745322 | Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition | Patrick Knebel, Kevin Safford, Rohit Bhatia | 2004-06-01 |
| 6678817 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine | Anuj Dua, James E. McCormick, Jr., Stephen R. Undy, Barry J. Arnold, David Carl Kubicek +1 more | 2004-01-13 |
| 6654849 | Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM | Kevin Liao | 2003-11-25 |
| 6643800 | Method and apparatus for testing microarchitectural features by using tests written in microcode | Kevin Safford, Patrick Knebel, Karl Brummel, M A Susith Rohana Fernando | 2003-11-04 |
| 6625759 | Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit | Jeremy Petsinger, Kevin Safford, Karl Brummel, Bruce Long, Patrick Knebel | 2003-09-23 |
| 6622241 | Method and apparatus for reducing branch prediction table pollution | Brian M. Kelly, Susith R. Fernando | 2003-09-16 |
| 6618801 | Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information | Patrick Knebel, Kevin Safford, Donald Soltis, Joel D. Lamb, Stephen R. Undy | 2003-09-09 |
| 6609247 | Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field | Anuj Dua, Susith R. Fernando, Kevin Safford | 2003-08-19 |
| 5956477 | Method for processing information in a microprocessor to facilitate debug and performance monitoring | Gregory L. Ranson, Gregg B. Lesartre, Douglas Benson Hunt, Steven T. Mangelsdorf | 1999-09-21 |
| 5956476 | Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns | Gregory L. Ranson, Robert E. Naas | 1999-09-21 |
| 5887003 | Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results | Gregory L. Ranson, Douglas Benson Hunt | 1999-03-23 |
| 5881217 | Input comparison circuitry and method for a programmable state machine | Gregory L. Ranson | 1999-03-09 |
| 5881224 | Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle | Gregory L. Ranson, Gregg B. Lesartre | 1999-03-09 |
| 5867644 | System and method for on-chip debug support and performance monitoring in a microprocessor | Gregory L. Ranson, John W. Bockhaus, Gregg B. Lesartre, Robert E. Naas, Jonathan Lotz +4 more | 1999-02-02 |
| 5784550 | Method for enhanced functional testing of a processor using dynamic trap handlers | Karl Brummel | 1998-07-21 |
| 5729554 | Speculative execution of test patterns in a random test generator | Duncan C. Weir | 1998-03-17 |
| 5437019 | Addressing method and apparatus for a computer system | — | 1995-07-25 |
| 5293607 | Flexible N-way memory interleaving | William S. Jaffe, William R. Bryg | 1994-03-08 |
| 5287477 | Memory-resource-driven arbitration | Leith L. Johnson, William S. Jaffe | 1994-02-15 |
| 5265223 | Preservation of priority in computer bus arbitration | William S. Jaffe | 1993-11-23 |
| 5257356 | Method of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer system | William S. Jaffe, Leith L. Johnson | 1993-10-26 |