Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8802577 | Method for manufacturing a semiconductor device using a nitrogen containing oxide layer | Hiroaki Niimi, Jarvis Benjamin Jacobs | 2014-08-12 |
| 8492291 | Formation of gate dielectrics with uniform nitrogen distribution | Hiroaki Niimi | 2013-07-23 |
| 7799649 | Method for forming multi gate devices using a silicon oxide masking layer | Hiroaki Niimi | 2010-09-21 |
| 7670913 | Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor substrate | Hiroaki Niimi | 2010-03-02 |
| 7459390 | Method for forming ultra thin low leakage multi gate devices | Hiroaki Niimi | 2008-12-02 |
| 7435651 | Method to obtain uniform nitrogen profile in gate dielectrics | Ajith Varghese, Terrence J. Riley | 2008-10-14 |
| 7393787 | Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment | Hiroaki Niimi, Mahalingam Nandakumar | 2008-07-01 |
| 6866974 | Semiconductor process using delay-compensated exposure | Keeho Kim, Jarvis Benjamin Jacobs | 2005-03-15 |
| 6803661 | Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography | Gautam Thakar, Cameron Gross, Eric A. Joseph | 2004-10-12 |
| 6762130 | Method of photolithographically forming extremely narrow transistor gate elements | Jarvis Benjamin Jacobs | 2004-07-13 |
| 6737325 | Method and system for forming a transistor having source and drain extensions | Manoj Mehrotra | 2004-05-18 |
| 6624068 | Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography | Gautam Thakar, Cameron Gross, Eric A. Joseph | 2003-09-23 |
| 6582973 | Method for controlling a semiconductor manufacturing process | Padmanabh Krishnagiri | 2003-06-24 |
| 6482688 | Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate | Chimin Hu, Amitabh Jain, Manoj Mehrotra | 2002-11-19 |
| 6362111 | Tunable gate linewidth reduction process | Robert J. Kraft, James B. Friedmann | 2002-03-26 |
| 6214736 | Silicon processing method | Antonio Rotondaro, Robert J. Kraft, Charlotte M. Appel, Rebecca J. Gale, Katherine E. Violette | 2001-04-10 |
| 6087220 | Stack etch method for flash memory devices | Daty M. Rogers, Cetin Kaya, Freidoon Mehrad, Men-Chee Chen | 2000-07-11 |