Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9141670 | Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators | Jeremy Branscome, Michael Corwin, Joseph I. Chamdani | 2015-09-22 |
| 8468151 | Methods and systems for hardware acceleration of database operations and queries based on multiple hardware accelerators | Jeremy Branscome, Joseph I. Chamdani | 2013-06-18 |
| 7433351 | Isolation of data, control, and management traffic in a storage area network | Joseph E. Pelissier, Vikas Deolaliker, Joseph I. Chamdani, Litko Chan, Gurumurthy D. Ramkumar | 2008-10-07 |
| 6918071 | Yield improvement through probe-based cache size reduction | Meera Kasinathan | 2005-07-12 |
| 6725336 | Dynamically allocated cache memory for a multi-processor unit | — | 2004-04-20 |
| 6553435 | DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains | Kevin Normoyle, Michael A. Csoppenszky, Jaybharat Boddu, Jui-Cheng Su, Alex S. Han +1 more | 2003-04-22 |
| 6535966 | System and method for using a page tracking buffer to reduce main memory latency in a computer system | Kevin Normoyle, Brian J. McGee | 2003-03-18 |
| 6496917 | Method to reduce memory latencies by performing two levels of speculation | Kevin Normoyle, Brian J. McGee, Meera Kasinathan, Anup K. Sharma, Sutikshan Bhutani | 2002-12-17 |
| 6477622 | Simplified writeback handling | Kevin Normoyle, Meera Kasinathan | 2002-11-05 |
| 6330662 | Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures | Sanjay Patel, Adam R. Talcott | 2001-12-11 |
| 6289441 | Method and apparatus for performing multiple branch predictions per cycle | Adam R. Talcott, Ramesh Panwar, Sanjay Patel | 2001-09-11 |
| 6263416 | Method for reducing number of register file ports in a wide instruction issue processor | — | 2001-07-17 |
| 6256729 | Method and apparatus for resolving multiple branches | Sanjay Patel, Adam R. Talcott, Ramesh Panwar | 2001-07-03 |
| 6256709 | Method for storing data in two-way set associative odd and even banks of a cache memory | Sanjay Patel, Ramesh Panwar, Adam R. Talcott | 2001-07-03 |
| 6134654 | Bi-level branch target prediction scheme with fetch address prediction | Sanjay Patel, Adam R. Talcott | 2000-10-17 |
| 6115810 | Bi-level branch target prediction scheme with mux select prediction | Sanjay Patel, Adam R. Talcott | 2000-09-05 |
| 5996048 | Inclusion vector architecture for a level two cache | Ricky C. Hetherington | 1999-11-30 |
| 5944810 | Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data | — | 1999-08-31 |
| 5938761 | Method and apparatus for branch target prediction | Sanjay Patel, Adam R. Talcott | 1999-08-17 |
| 5884100 | Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor | Kevin Normoyle, Michael A. Csoppenszky, Jaybharat Boddu, Jui-Cheng Su, Alex S. Han +1 more | 1999-03-16 |
| 5860117 | Apparatus and method to improve primary memory latencies using an eviction buffer to store write requests | — | 1999-01-12 |
| 5854761 | Cache memory array which stores two-way set associative data | Sanjay Patel, Ramesh Panwar, Adam R. Talcott | 1998-12-29 |
| 5835947 | Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses | — | 1998-11-10 |
| 5829010 | Apparatus and method to efficiently abort and restart a primary memory access | — | 1998-10-27 |
| 5761708 | Apparatus and method to speculatively initiate primary memory accesses | Anuradha N. Moudgal, Kevin Normoyle | 1998-06-02 |