Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188696 | Method, system, and product for deferred merge based method for graph based analysis pessimism reduction | Amit Dhuria, Sri Harsha POTHUKUCHI, Pradeep Yadav, Igor Keller, Sharad Mehrotra +2 more | 2021-11-30 |
| 10467365 | Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design | Vibhor Garg | 2019-11-05 |
| 10460059 | System and method for generating reduced standard delay format files for gate level simulation | Akash Khandelwal, Rajarshi Mukherjee, Chih-kuo Yu | 2019-10-29 |
| 10169501 | Timing context generation with multi-instance blocks for hierarchical analysis | Amit Dhuria | 2019-01-01 |
| 10133842 | Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs | Amit Dhuria, Krishna Belkhale, Saulius Kersulis | 2018-11-20 |
| 10037394 | Hierarchical timing analysis for multi-instance blocks | Amit Dhuria | 2018-07-31 |
| 8745561 | System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design | Vibhor Garg, Krishna Belkhale, Hakan Yalcin | 2014-06-03 |
| 7647220 | Transistor-level timing analysis using embedded simulation | Robert J. Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin | 2010-01-12 |