SP

Sri Harsha POTHUKUCHI

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
JPMorgan Chase: 1 patents #1,456 of 3,768Top 40%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,354,342 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11902469 Method for managing call queues for recurring customer questions Rudolph Mappus, Angel VINCENT, Peter KUTCHEN, Owen CHURCHILL, Jose BURGOS 2024-02-13
11188696 Method, system, and product for deferred merge based method for graph based analysis pessimism reduction Amit Dhuria, Pradeep Yadav, Pawan Kulshreshtha, Igor Keller, Sharad Mehrotra +2 more 2021-11-30
11003821 Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits Amit Dhuria 2021-05-11