VG

Vibhor Garg

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
📍 Union City, CA: #403 of 1,177 inventorsTop 35%
🗺 California: #124,610 of 386,348 inventorsTop 35%
Overall (All Time): #1,155,067 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
11144698 Method, system, and product for an improved approach to placement and optimization in a physical design flow Edward J. Martinage, Amit Dhuria, Krishna Belkhale 2021-10-12
10990733 Shared timing graph propagation for multi-mode multi-corner static timing analysis Amit Dhuria 2021-04-27
10467365 Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design Pawan Kulshreshtha 2019-11-05
8745561 System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design Krishna Belkhale, Pawan Kulshreshtha, Hakan Yalcin 2014-06-03