Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2025-09-02 |
| 12386506 | Tagged memory operated at lower VMIN in error tolerant system | Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2025-08-12 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Harsh Rawat, Promod Kumar, Kedar Janardan Dhori, Manuj AYODHYAWASI | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Kedar Janardan Dhori +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI, Harsh Rawat | 2025-07-08 |
| 12292780 | Computing system power management device, system and method | Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar | 2025-05-06 |
| 12243584 | In-memory compute array with integrated bias elements | Anuj Grover, Tanmoy Roy | 2025-03-04 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Harsh Rawat, Promod Kumar, Manuj AYODHYAWASI | 2025-02-25 |
| 12183424 | Bit-cell architecture based in-memory compute | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-12-31 |
| 12176025 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-12-24 |
| 12170120 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Hitesh Chawla, Tanuj KUMAR, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori +2 more | 2024-12-17 |
| 12118451 | Deep convolutional network heterogeneous architecture | Giuseppe Desoli, Thomas Boesch, Surinder Singh, Elio Guidetti, Fabio Giuseppe DE AMBROGGI +2 more | 2024-10-15 |
| 12087356 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-09-10 |
| 11984151 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2024-05-14 |
| 11900240 | Variable clock adaptation in neural network processors | Giuseppe Desoli, Manuj AYODHYAWASI, Thomas Boesch, Surinder Singh | 2024-02-13 |
| 11836346 | Tagged memory operated at lower vmin in error tolerant system | Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2023-12-05 |
| 11829730 | Elements for in-memory compute | Tanmoy Roy, Anuj Grover, Giuseppe Desoli | 2023-11-28 |
| 11823771 | Streaming access memory device, system and method | Thomas Boesch, Anuj Grover, Surinder Singh, Giuseppe Desoli | 2023-11-21 |
| 11749343 | Memory management device, system and method | Tanmoy Roy, Anuj Grover | 2023-09-05 |
| 11726543 | Computing system power management device, system and method | Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar | 2023-08-15 |
| 11605424 | In-memory compute array with integrated bias elements | Anuj Grover, Tanmoy Roy | 2023-03-14 |
| 11474788 | Elements for in-memory compute | Tanmoy Roy, Anuj Grover, Giuseppe Desoli | 2022-10-18 |
| 11360667 | Tagged memory operated at lower vmin in error tolerant system | Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2022-06-14 |
| 11257543 | Memory management device, system and method | Tanmoy Roy, Anuj Grover | 2022-02-22 |
| 11094376 | In-memory compute array with integrated bias elements | Anuj Grover, Tanmoy Roy | 2021-08-17 |