Issued Patents All Time
Showing 1–25 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333357 | Memory bit cell for in-memory computation | Michael A. Dreesen, Ajay Bhatia, Greg M. Hess, Siddhesh Gaiki | 2025-06-17 |
| 12216161 | Scan chain analysis using predefined capture signature | Bo Yang, Antonietta Oliva, Vasu P. Ganti, Vijay M. Bettada | 2025-02-04 |
| 12072810 | System control using sparse data | Ben D. Jarrett, Edward M. McCombs, Greg M. Hess | 2024-08-27 |
| 12066938 | Data pattern based cache management | — | 2024-08-20 |
| 11803480 | System control using sparse data | Ben D. Jarrett, Edward M. McCombs, Greg M. Hess | 2023-10-31 |
| 11755480 | Data pattern based cache management | — | 2023-09-12 |
| 11442855 | Data pattern based cache management | — | 2022-09-13 |
| 11327896 | System control using sparse data | Ben D. Jarrett, Edward M. McCombs, Greg M. Hess | 2022-05-10 |
| 10838483 | Level shifter with isolation on both input and output domains with enable from both domains | Vivekanandan Venugopal, Ajay Bhatia | 2020-11-17 |
| 10812081 | Output signal control during retention mode operation | Michael A. Dreesen | 2020-10-20 |
| 10691610 | System control using sparse data | Ben D. Jarrett, Edward M. McCombs, Greg M. Hess | 2020-06-23 |
| 10491197 | Flop circuit with integrated clock gating circuit | Vivekanandan Venugopal, Ajay Bhatia | 2019-11-26 |
| 10461747 | Low power clock gating circuit | Vivekanandan Venugopal, Ajay Bhatia | 2019-10-29 |
| 10191086 | Power detection circuit | Zhao-Jun Wang, Ajay Bhatia | 2019-01-29 |
| 10187061 | Level shifting circuit with data resolution and grounded input nodes | Vivekanandan Venugopal, Ajay Bhatia | 2019-01-22 |
| 10177051 | Transistor work function adjustment by laser stimulation | — | 2019-01-08 |
| 10033356 | Reduced power set-reset latch based flip-flop | Zhao-Jun Wang, Sheela R. Shreedharan, Ajay Bhatia | 2018-07-24 |
| 10008423 | Transistor work function adjustment by laser stimulation | — | 2018-06-26 |
| 9488692 | Mode based skew to reduce scan instantaneous voltage drop and peak currents | Asad A. Bawa, Benjamin A. Marrou, Christopher Ng, Mihir S. Sabnis, Zameeruddin Mohammed +1 more | 2016-11-08 |
| 9453879 | On-die system for monitoring and predicting performance | Brian S. Leibowitz, Mohamed H. Abu-Rahma | 2016-09-27 |
| 9412469 | Weak bit detection using on-die voltage modulation | Michael A. Dreesen, Edward M. McCombs | 2016-08-09 |
| 9201993 | Goal-driven search of a stochastic process using reduced sets of simulation points | — | 2015-12-01 |
| 9177671 | Memory with bit line capacitive loading | Michael E. Runas | 2015-11-03 |
| 9076556 | Memory with bit line current injection | Michael E. Runas | 2015-07-07 |
| 9013933 | Memory with redundant sense amplifier | Michael E. Runas | 2015-04-21 |