Issued Patents All Time
Showing 51–75 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6262583 | Test socket and methods | Chris G. Martin | 2001-07-17 |
| 6259621 | Method and apparatus for minimization of data line coupling in a semiconductor memory device | Wen Li | 2001-07-10 |
| 6236116 | Semiconductor device having a built-in heat sink and process of manufacturing same | — | 2001-05-22 |
| 6232148 | Method and apparatus leads-between-chips | Jeffrey D. Bruce, Darryl L. Habersetzer, Gordon D. Roberts, James E. Miller | 2001-05-15 |
| 6226210 | Method of detecting a short from a digit line pair to ground | Kurt D. Beigel, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce +1 more | 2001-05-01 |
| 6226221 | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts | Brian M. Shirley | 2001-05-01 |
| 6208018 | Piggyback multiple dice assembly | Jeffrey D. Bruce | 2001-03-27 |
| 6204537 | ESD protection scheme | — | 2001-03-20 |
| 6198676 | Test device | Kurt D. Beigel, Douglas J. Cutter, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +2 more | 2001-03-06 |
| 6194235 | Method of fabricating and testing an embedded semiconductor device | — | 2001-02-27 |
| 6188622 | Method of identifying a defect within a memory circuit | Kurt D. Beigel, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce +1 more | 2001-02-13 |
| 6181617 | Method and apparatus for testing a semiconductor device | Kurt D. Beigel, Douglas J. Cutter, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +2 more | 2001-01-30 |
| 6157204 | Buffer with adjustable slew rate and a method of providing an adjustable slew rate | Joseph C. Sher | 2000-12-05 |
| 6137664 | Well resistor for ESD protection of CMOS circuits | Stephen L. Casper, Joseph C. Sher | 2000-10-24 |
| 6118291 | Test socket and methods | Chris G. Martin | 2000-09-12 |
| 6111806 | Memory device with regulated power supply control | Brian M. Shirley, Gordon D. Roberts | 2000-08-29 |
| 6078538 | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts | Brian M. Shirley | 2000-06-20 |
| 6068892 | Methods and structures for pad reconfiguration to allow intermediate testing during manufacture of an integrated circuit | — | 2000-05-30 |
| 6069492 | Voltage compensating CMOS input buffer circuit | Joseph C. Sher | 2000-05-30 |
| 6069506 | Method and apparatus for improving the performance of digital delay locked loop circuits | James E. Miller, Aaron Schoenfeld, R. Jacob Baker | 2000-05-30 |
| 6066548 | Advance metallization process | Trung T. Doan, Jeff Zhiqiang Wu | 2000-05-23 |
| 6060896 | Super-voltage circuit with a fast reset | Joseph C. Sher | 2000-05-09 |
| 6054334 | Methods and structures for pad reconfiguration to allow intermediate testing during manufacture of an integrated circuit | — | 2000-04-25 |
| 6052322 | Memory circuit voltage regulator | Kurt D. Beigel, Douglas J. Cutter, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +2 more | 2000-04-18 |
| 6040733 | Two-stage fusible electrostatic discharge protection circuit | Stephen L. Casper | 2000-03-21 |