Issued Patents All Time
Showing 101–114 of 114 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5801421 | Staggered contact placement on CMOS chip | Joseph C. Sher, Stephen L. Casper | 1998-09-01 |
| 5770480 | Method of leads between chips assembly | Jeffrey D. Bruce, Daryl L. Habersetzer, Gordon D. Roberts, James E. Miller | 1998-06-23 |
| 5767552 | Structure for ESD protection in semiconductor chips | Stephen L. Casper, Joseph C. Sher | 1998-06-16 |
| 5729047 | Method and structure for providing signal isolation and decoupling in an integrated circuit device | — | 1998-03-17 |
| 5721658 | Input/output electrostatic discharge protection for devices with multiple individual power groups | Jeffrey P. Wright | 1998-02-24 |
| 5712575 | Super-voltage circuit with a fast reset | Joseph C. Sher | 1998-01-27 |
| 5679593 | Method of fabricating a high resistance integrated circuit resistor | James E. Miller | 1997-10-21 |
| 5677567 | Leads between chips assembly | Jeffrey D. Bruce, Daryl L. Habersetzer, Gordon D. Roberts, James E. Miller | 1997-10-14 |
| 5666067 | Voltage compensating CMOS input buffer circuit | Joseph C. Sher | 1997-09-09 |
| 5663919 | Memory device with regulated power supply control | Brian M. Shirley, Gordon D. Roberts | 1997-09-02 |
| 5661428 | Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit | Wen Li | 1997-08-26 |
| 5656967 | Two-stage fusible electrostatic discharge protection circuit | Stephen L. Casper | 1997-08-12 |
| 5654860 | Well resistor for ESD protection of CMOS circuits | Stephen L. Casper, Joseph C. Sher | 1997-08-05 |
| 5578941 | Voltage compensating CMOS input buffer circuit | Joseph C. Sher | 1996-11-26 |