Issued Patents All Time
Showing 25 most recent of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10754653 | Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy | Sergei Larin, Anshuman Das Gupta | 2020-08-25 |
| 10474461 | Instruction-based synchronization of operations including at least one SIMD scatter operation | Eric W. Mahurin | 2019-11-12 |
| 10437591 | Executing an operating system on processors having different instruction set architectures | Michael McDonald, Erich James Plondke, Pavel Potoplyak, Richard Lee-Chee Kuo, Bryan C. Bayerdorffer | 2019-10-08 |
| 10289412 | Floating point constant generation instruction | Erich James Plondke, Charles Joseph Tabony, Swaminathan Balasubramanian | 2019-05-14 |
| 10133598 | Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to schedule virtual processors for guest operating systems | Erich James Plondke | 2018-11-20 |
| 10120692 | Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form | Sergei Larin, Anshuman Das Gupta | 2018-11-06 |
| 10114756 | Externally programmable memory management unit | Christopher Edward Koob, Erich James Plondke, Piyush Patel, Thomas Andrew Sartorius | 2018-10-30 |
| 10055227 | Using the least significant bits of a called function's address to switch processor modes | Charles Joseph Tabony, Erich James Plondke, Suresh K. Venkumahanti, Evandro Menezes | 2018-08-21 |
| 10025711 | Hybrid write-through/write-back cache policy managers, and related systems and methods | Peter G. Sassone, Christopher Edward Koob, Dana Michelle Vantrease, Suresh K. Venkumahanti | 2018-07-17 |
| 9823928 | FIFO load instruction | Mao Zeng, Erich James Plondke, Ajay Anant Ingle | 2017-11-21 |
| 9824013 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors | Christopher Edward Koob, Ajay Anant Ingle, Suresh K. Venkumahanti | 2017-11-21 |
| 9785434 | Fast minimum and maximum searching instruction | Erich James Plondke, Mao Zeng, Swaminathan Balasubramanian, David Hoyle | 2017-10-10 |
| 9715392 | Multiple clustered very long instruction word processing core | Suresh K. Venkumahanti, Ankit Ghiya, Peter G. Sassone, Suman Mamidi | 2017-07-25 |
| 9678758 | Coprocessor for out-of-order loads | Christopher Edward Koob, Eric W. Mahurin, Suresh K. Venkumahanti | 2017-06-13 |
| 9678754 | System and method of processing hierarchical very long instruction packets | Erich James Plondke, Ajay Anant Ingle, Suresh K. Venkumahanti, Charles Joseph Tabony | 2017-06-13 |
| 9632781 | Vector register addressing and functions based on a scalar register data value | Ajay Anant Ingle, Marc Hoffman, Jose Fridman | 2017-04-25 |
| 9626579 | Increasing canny filter implementation speed | Kim-Chyan Gan, Mao Zeng | 2017-04-18 |
| 9606818 | Systems and methods of executing multiple hypervisors using multiple sets of processors | Erich James Plondke, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius | 2017-03-28 |
| 9455743 | Dedicated arithmetic encoding instruction | Bo Zhou, Mao Zeng, Erich James Plondke, Shu Xiao, Junchen Du +1 more | 2016-09-27 |
| 9396012 | Systems and methods of using a hypervisor with guest operating systems and virtual processors | Erich James Plondke | 2016-07-19 |
| 9367468 | Data cache way prediction | Peter G. Sassone, Suresh K. Venkumahanti | 2016-06-14 |
| 9361109 | System and method to evaluate a data value as an instruction | Erich James Plondke, Suresh K. Venkumahanti | 2016-06-07 |
| 9304932 | Instruction cache having a multi-bit way prediction mask | Peter G. Sassone, Suresh K. Venkumahanti | 2016-04-05 |
| 9235418 | Register files for a digital signal processor operating in an interleaved multi-threaded environment | Muhammad Ahmed, Erich James Plondke, William C. Anderson | 2016-01-12 |
| 9207943 | Real time multithreaded scheduler and scheduling method | Erich James Plondke | 2015-12-08 |