Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8051397 | Method and system for conducting design explorations of an integrated circuit | Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Patrick John Eichenseer | 2011-11-01 |
| 7930675 | Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis | Oleg Levitsky, Wilson Chan, Dongzi Liu | 2011-04-19 |
| 7853905 | Performing early DFT-aware prototyping of a design | Ping-Chih Wu, Weibin Ding, Louis Liu, Yiqun Ding | 2010-12-14 |
| 7603643 | Method and system for conducting design explorations of an integrated circuit | Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Patrick John Eichenseer | 2009-10-13 |
| 6651235 | Scalable, partitioning integrated circuit layout system | Wei-Jin Dai, Hsi-Chuan Chen, Wei-Lun Kao | 2003-11-18 |
| 6578183 | Method for generating a partitioned IC layout | Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer | 2003-06-10 |