Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840924 | Phase interpolator | Steven G. Wurzer, Neil Petrie, Kevin R. Duncan | 2020-11-17 |
| 10425090 | Phase interpolator | Steven G. Wurzer, Neil Petrie, Kevin R. Duncan | 2019-09-24 |
| 10153775 | Phase interpolator | Steven G. Wurzer, Neil Petrie, Kevin R. Duncan | 2018-12-11 |
| 7076410 | Method and apparatus for efficiently viewing a number of selected components using a database editor tool | James E. Rezek | 2006-07-11 |
| 6910200 | Method and apparatus for associating selected circuit instances and for performing a group operation thereon | Mark D. Aubel, James M. Nead, James E. Rezek | 2005-06-21 |
| 6889370 | Method and apparatus for selecting and aligning cells using a placement tool | James E. Rezek | 2005-05-03 |
| 6701289 | Method and apparatus for using a placement tool to manipulate cell substitution lists | Robert E. Garnett, James E. Rezek, Mark D. Aubel | 2004-03-02 |
| 6684376 | Method and apparatus for selecting components within a circuit design database | James E. Rezek, Mark D. Aubel, Merwin H. Alferness | 2004-01-27 |
| 6546532 | Method and apparatus for traversing and placing cells using a placement tool | James E. Rezek | 2003-04-08 |
| 6516456 | Method and apparatus for selectively viewing nets within a database editor tool | Robert E. Garnett, James E. Rezek, Mark D. Aubel | 2003-02-04 |
| 6029205 | System architecture for improved message passing and process synchronization between concurrently executing processes | Merwin H. Alferness, Mark D. Aubel, Charles R. Caldarale, James W. Douglas, David C. Johnson +7 more | 2000-02-22 |
| 5912820 | Method and apparatus for distributing a clock tree within a hierarchical circuit design | James E. Rezek, John T. Rusterholz | 1999-06-15 |
| 5726903 | Method and apparatus for resolving conflicts between cell substitution recommendations provided by a drive strength adjust tool | Douglas A. Fuller | 1998-03-10 |
| 5724250 | Method and apparatus for performing drive strength adjust optimization in a circuit design | Kenneth L. Engelbrecht, Robert J. Palermo, Douglas A. Fuller | 1998-03-03 |
| 5719783 | Method and apparatus for performing timing analysis on a circuit design | Duane G. Kurth, Douglas A. Fuller | 1998-02-17 |
| 5696693 | Method for placing logic functions and cells in a logic design using floor planning by analogy | Mark D. Aubel, Arthur F. Boehm, James E. Rezek, John T. Rusterholz, Richard F. Paul | 1997-12-09 |
| 5611065 | Address prediction for relative-to-absolute addressing | Merwin H. Alferness, John Z. Nguyen | 1997-03-11 |
| 5577259 | Instruction processor control system using separate hardware and microcode control signals to control the pipelined execution of multiple classes of machine instructions | Merwin H. Alferness, John S. Kuslak, Mark A. Vasquez, Eric Collins | 1996-11-19 |
| 5555396 | Hierarchical queuing in a system architecture for improved message passing and process synchronization | Merwin H. Alferness, Charles R. Caldarale, David R. Johnson, James R. McBreen | 1996-09-10 |