Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10255196 | Method and apparatus for sub-page write protection | Vedvyas Shanbhogue, Christopher D. Bryant | 2019-04-09 |
| 9323942 | Protecting information processing system secrets from debug attacks | Vedvyas Shanbhogue, Jason W. Brandt | 2016-04-26 |
| 9141386 | Vector logical reduction operation implemented using swizzling on a semiconductor chip | Sridhar Samudrala, Roger Golliver | 2015-09-22 |
| 9092213 | Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation | Sridhar Samudrala, Roger Golliver, Eric W. Mahurin | 2015-07-28 |
| 9063860 | Method and system for optimizing prefetching of cache memory lines | Leigang Kou, Mike Filippo | 2015-06-23 |
| 8955144 | Protecting information processing system secrets from debug attacks | Vedvyas Shanbhogue, Jason W. Brandt | 2015-02-10 |
| 8667042 | Functional unit for vector integer multiply add instruction | Sridhar Samudrala, Roger Golliver | 2014-03-04 |
| 8301907 | Supporting advanced RAS features in a secured computing system | Mahesh S. Natu, Sham M. Datta, James Vash, Sailesh Kottapalli, Scott P. Bobholz +1 more | 2012-10-30 |