Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046289 | Sub-block status dependent device operation | Guirong Liang | 2024-07-23 |
| 11972810 | Read pass voltage dependent recovery voltage setting between program and program verify | Wei Zhao, Henry Chin | 2024-04-30 |
| 11914933 | Generation of dynamic design flows for integrated circuits | — | 2024-02-27 |
| 11854620 | Word line zoned adaptive initial program voltage for non-volatile memory | Erika Penzo, Henry Chin | 2023-12-26 |
| 11630930 | Generation of dynamic design flows for integrated circuits | — | 2023-04-18 |
| 11521691 | Triggering next state verify in program loop for nonvolatile memory | Hua-Ling Cynthia Hsu, Henry Chin, Erika Penzo, Fanglin Zhang | 2022-12-06 |
| 11139031 | Neighbor word line compensation full sequence program scheme | Guirong Liang, Henry Chin | 2021-10-05 |
| 11055457 | Pad ring generation for integrated circuits | John Drummond | 2021-07-06 |
| 11048837 | Generation of dynamic design flows for integrated circuits | — | 2021-06-29 |
| 10964402 | Reprogramming memory cells to tighten threshold voltage distributions and improve data retention | Henry Chin, Ashish Baraskar | 2021-03-30 |
| 10957394 | NAND string pre-charge during programming by injecting holes via substrate | Wei Zhao, Henry Chin | 2021-03-23 |
| 10922462 | Intellectual property block validation and design integration for integrated circuits | — | 2021-02-16 |
| 10636501 | Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line | Ching-Huang Lu, Vinh Diep, Changyuan Chen | 2020-04-28 |
| 10541035 | Read bias adjustment for compensating threshold voltage shift due to lateral charge movement | Ching-Huang Lu, Chung-Yao Pai, Yingda Dong | 2020-01-21 |
| 9318204 | Non-volatile memory and method with adjusted timing for individual programming pulses | Man Lung Mui, Kou Tei | 2016-04-19 |
| 7153744 | Method of forming self-aligned poly for embedded flash | Chung-Yi Yu | 2006-12-26 |
| 6849499 | Process for flash memory cell | Hung-Cheng Sung, Cheng-Yuan Hsu | 2005-02-01 |
| 6828183 | Process for high voltage oxide and select gate poly for split-gate flash memory | Hung-Cheng Sung, Cheng-Yuan Hsu | 2004-12-07 |
| 6819593 | Architecture to suppress bit-line leakage | Der-Shin Shyu, Hung-Cheng Sung, Li-Wen Chang, Chen-Ming Huang, Ya-Chen Kao | 2004-11-16 |
| 6781363 | Memory sorting method and apparatus | — | 2004-08-24 |
| 6675319 | Memory access and data control | — | 2004-01-06 |
| 6649489 | Poly etching solution to improve silicon trench for low STI profile | Li-Wen Chang, Hung-Cheng Sung, Der-Shin Shyu, Chen-Ming Huang, Ya-Chen Kao | 2003-11-18 |
| 6569736 | Method for fabricating square polysilicon spacers for a split gate flash memory device by multi-step polysilicon etch | Cheng-Yuan Hsu, Hung-Cheng Sung, Su-Chang Chen, Chia-Ta Hsieh, Der-Shin Shyu | 2003-05-27 |
| 6482700 | Split gate field effect transistor (FET) device with enhanced electrode registration and method for fabrication thereof | Hung-Cheng Sung | 2002-11-19 |
| 6358827 | Method of forming a squared-off, vertically oriented polysilicon spacer gate | Hung-Chen Sung, Cheng-Yuan Hsu | 2002-03-19 |