GR

George V. Rouse

Harris: 17 patents #60 of 2,288Top 3%
IA Intersil Americas: 7 patents #161 of 468Top 35%
FS Fairchild Semiconductor: 1 patents #419 of 715Top 60%
Overall (All Time): #165,624 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7052973 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone Jack H. Linn, William H. Speece, Michael G. Shlepr 2006-05-30
6909146 Bonded wafer with metal silicidation Jack H. Linn, Robert K. Lowry, James F. Buller 2005-06-21
6825532 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone Jack H. Linn, William H. Speece, Michael G. Shlepr 2004-11-30
6812108 BICMOS process with low temperature coefficient resistor (TCRL) Donald F. Hemmenway, Jose Avelino Delgado, John Butler, Anthony L. Rivoli, Michael D. Church +2 more 2004-11-02
6798024 BiCMOS process with low temperature coefficient resistor (TCRL) Donald F. Hemmenway, Jose Avelino Delgado, John Butler, Anthony L. Rivoli, Michael D. Church +2 more 2004-09-28
6455379 Power trench transistor device source region formation using silicon spacer Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn 2002-09-24
6255195 Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method Jack H. Linn, William H. Speece, Michael G. Shlepr 2001-07-03
6246090 Power trench transistor device source region formation using silicon spacer Linda S. Brush, Jun Zeng, John J. Hackenberg, Jack H. Linn 2001-06-12
5932022 SC-2 based pre-thermal treatment wafer cleaning process Jack H. Linn, Sana Rafie, Roberta R. Nolan-Lobmeyer, Diana L. Hackenberg, Steven T. Slasor +1 more 1999-08-03
5849627 Bonded wafer processing with oxidative bonding Jack H. Linn, Robert K. Lowry, James F. Buller 1998-12-15
5744852 Bonded wafer Jack H. Linn, George Bajor 1998-04-28
5603779 Bonded wafer and method of fabrication thereof Jack H. Linn, George Bajor 1997-02-18
5569620 Bonded wafer processing with metal silicidation Jack H. Linn, Robert K. Lowry, James F. Buller 1996-10-29
5517047 Bonded wafer processing Jack H. Linn, Robert K. Lowry, James F. Buller, William H. Speece 1996-05-14
5387555 Bonded wafer processing with metal silicidation Jack H. Linn, Robert K. Lowry, James F. Buller 1995-02-07
5362667 Bonded wafer processing Jack H. Linn, Robert K. Lowry, James F. Buller, William H. Speece 1994-11-08
5334273 Wafer bonding using trapped oxidizing vapor John P. Short, Craig J. McLachlan, James R. Zibrida 1994-08-02
5266135 Wafer bonding process employing liquid oxidant John P. Short, Craig J. McLachlan, James R. Zibrida 1993-11-30
5240876 Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process Stephen Joseph Gaul 1993-08-31
5218213 SOI wafer with sige Stephen Joseph Gaul 1993-06-08
5091331 Ultra-thin circuit fabrication by controlled wafer debonding Jose Avelino Delgado, Stephen Joseph Gaul, Craig J. McLachlan 1992-02-25
5081061 Manufacturing ultra-thin dielectrically isolated wafers Paul S. Reinecke 1992-01-14
5034343 Manufacturing ultra-thin wafer using a handle wafer Paul S. Reinecke, Craig J. McLachlan 1991-07-23
4968628 Method of fabricating back diffused bonded oxide substrates Jose Avelino Delgado, Stephen Joseph Gaul, Craig J. McLachlan 1990-11-06
4851078 Dielectric isolation process using double wafer bonding John P. Short 1989-07-25