Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812108 | BICMOS process with low temperature coefficient resistor (TCRL) | Donald F. Hemmenway, John Butler, Anthony L. Rivoli, Michael D. Church, George V. Rouse +2 more | 2004-11-02 |
| 6798024 | BiCMOS process with low temperature coefficient resistor (TCRL) | Donald F. Hemmenway, John Butler, Anthony L. Rivoli, Michael D. Church, George V. Rouse +2 more | 2004-09-28 |
| 6492705 | Integrated circuit air bridge structures and methods of fabricating same | Patrick A. Begley, William R. Young, Anthony L. Rivoli, Stephen Joseph Gaul | 2002-12-10 |
| 6351021 | Low temperature coefficient resistor (TCRL) | Donald F. Hemmenway, John Butler, Anthony L. Rivoli | 2002-02-26 |
| 6274460 | Defect gettering by induced stress | Craig J. McLachlan | 2001-08-14 |
| 6211056 | Integrated circuit air bridge structures and methods of fabricating same | Patrick A. Begley, William R. Young, Anthony L. Rivoli, Stephen Joseph Gaul | 2001-04-03 |
| 6114768 | Surface mount die by handle replacement | Stephen Joseph Gaul | 2000-09-05 |
| 5949144 | Pre-bond cavity air bridge | Stephen Joseph Gaul | 1999-09-07 |
| 5929508 | Defect gettering by induced stress | Craig J. McLachlan | 1999-07-27 |
| 5825092 | Integrated circuit with an air bridge having a lid | Stephen Joseph Gaul | 1998-10-20 |
| 5807783 | Surface mount die by handle replacement | Stephen Joseph Gaul | 1998-09-15 |
| 5773891 | Integrated circuit method for and structure with narrow line widths | Stephen Joseph Gaul | 1998-06-30 |
| 5639688 | Method of making integrated circuit structure with narrow line widths | Stephen Joseph Gaul | 1997-06-17 |
| 5091331 | Ultra-thin circuit fabrication by controlled wafer debonding | Stephen Joseph Gaul, George V. Rouse, Craig J. McLachlan | 1992-02-25 |
| 4968628 | Method of fabricating back diffused bonded oxide substrates | Stephen Joseph Gaul, Craig J. McLachlan, George V. Rouse | 1990-11-06 |
| 4897362 | Double epitaxial method of fabricating semiconductor devices on bonded wafers | George Bajor | 1990-01-30 |