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Prefetch store filtering |
Luca MARONCELLI, Cedric Denis Robert Airaud, Peter Raphael Eid |
2024-11-12 |
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Methods and apparatus for predicting instructions for execution |
Guillaume Bolbenes, Thibaut Elie Lanois, Houdhaifa BOUZGUARROU |
2024-02-13 |
| 11138119 |
Increasing effective cache associativity |
Damien Guillaume Pierre Payet, Natalya Bondarenko, Lucas Garcia |
2021-10-05 |
| 11086781 |
Methods and apparatus for monitoring prefetcher accuracy information using a prefetch flag independently accessible from prefetch tag information |
Natalya Bondarenko, Nathanael Premillieu, Pierre Marcel Laurent |
2021-08-10 |
| 10528355 |
Handling move instructions via register renaming or writing to a different physical register using control flags |
Chris Abernathy |
2020-01-07 |
| 9542194 |
Speculative register file read suppression |
Chris Abernathy, Michael Filippo |
2017-01-10 |
| 9513925 |
Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed state |
Nicolas Chaussade, Melanie Emanuelle Lucie Teyssier, Rémi Marius Teyssier, Jocelyn Francois Orion Jaubert |
2016-12-06 |
| 9189432 |
Apparatus and method for predicting target storage unit |
Melanie Emanuelle Lucie Teyssier, Jocelyn Francois Orion Jaubert, Nicolas Jean Phillippe Huot |
2015-11-17 |
| 8769251 |
Data processing apparatus and method for converting data values between endian formats |
Philippe Luc, Norbert Bernard Eugene Lataille, Nicolas Chaussade |
2014-07-01 |
| 8578139 |
Checkpointing long latency instruction as fake branch in branch prediction mechanism |
Nicolas Chaussade, Melanie Emanuelle Lucie Teyssier, Rémi Marius Teyssier, Jocelyn Francois Orion Jaubert |
2013-11-05 |
| 8458532 |
Error handling mechanism for a tag memory within coherency control circuitry |
Jocelyn Francois Orion Jaubert, Melanie Emanuelle Lucie Teyssier |
2013-06-04 |
| 8352794 |
Control of clock gating |
Rémi Marius Teyssier, Jocelyn Francois Orion Jaubert, Cedric Denis Robert Airaud |
2013-01-08 |
| 7941608 |
Cache eviction |
Philippe Luc, Elodie Charra, Nicolas Chaussade |
2011-05-10 |
| 7925868 |
Suppressing register renaming for conditional instructions predicted as not executed |
Norbert Bernard Eugene Lataille, Cedric Denis Robert Airaud, Melanie Emanuelle Lucie Vincent |
2011-04-12 |
| 7844800 |
Method for renaming a large number of registers in a data processing system using a background channel |
Melanie Emanuelle Lucie Vincent, Cedric Denis Robert Airaud, Norbert Bernard Eugene Lataille |
2010-11-30 |
| 7624253 |
Determining register availability for register renaming |
Cedric Denis Robert Airaud, Norbert Bernard Eugene Lataille, Melanie Emanuelle Lucie Vincent |
2009-11-24 |
| 7600077 |
Cache circuitry, data processing apparatus and method for handling write access requests |
Philippe Luc, Elodie Charra, Nicolas Chaussade |
2009-10-06 |
| 7590826 |
Speculative data value usage |
Philippe Jean-Pierre Raphalen, Norbert Bernard Eugene Lataille, Frederic Claude Marie Piry |
2009-09-15 |
| 7587556 |
Store buffer capable of maintaining associated cache information |
Frederic Claude Marie Piry, Philippe Jean-Pierre Raphalen, Gilles Eric Grandou |
2009-09-08 |
| 7568072 |
Cache eviction |
Philippe Luc, Elodie Charra, Nicolas Chaussade |
2009-07-28 |
| 7552285 |
Line fill techniques |
Nicolas Chaussade, Elodie Charra, Philippe Luc |
2009-06-23 |
| 7533241 |
Variable size cache memory support within an integrated circuit |
Vladimir Vasekin, Andrew Christophe Rose, Nicolas Chaussade |
2009-05-12 |