Issued Patents All Time
Showing 1–25 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6764904 | Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings | Yowjuang W. Liu | 2004-07-20 |
| 6667227 | Trenched gate metal oxide semiconductor device and method | Yowjuang W. Liu | 2003-12-23 |
| 6664797 | Method for profiling semiconductor device junctions using a voltage contrast scanning electron microscope | — | 2003-12-16 |
| 6627952 | Silicon oxide insulator (SOI) semiconductor having selectively linked body | — | 2003-09-30 |
| 6515344 | Thin oxide anti-fuse | — | 2003-02-04 |
| 6417030 | Leaky lower interface for reduction of floating body effect in SOI devices | Matthew S. Buynoski | 2002-07-09 |
| 6395437 | Junction profiling using a scanning voltage micrograph | — | 2002-05-28 |
| 6348356 | Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors | Sunil N. Shabde, Richard C. Blish, II | 2002-02-19 |
| 6309919 | Method for fabricating a trench-gated vertical CMOS device | Yowjuang W. Liu | 2001-10-30 |
| 6285054 | Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings | Yowjuang W. Liu | 2001-09-04 |
| 6271151 | Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process | — | 2001-08-07 |
| 6242329 | Method for manufacturing asymmetric channel transistor | Carl Robert Huster, Concetta Riccobene, Richard P. Rouse | 2001-06-05 |
| 6225161 | Fully recessed semiconductor method for low power applications with single wrap around buried drain region | Yowjuang W. Liu | 2001-05-01 |
| 6225667 | Leaky lower interface for reduction of floating body effect in SOI devices | Matthew S. Buynoski | 2001-05-01 |
| 6215155 | Silicon-on-insulator configuration which is compatible with bulk CMOS architecture | — | 2001-04-10 |
| 6204516 | Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors | Sunil N. Shabde, Richard C. Blish, II | 2001-03-20 |
| 6201761 | Field effect transistor with controlled body bias | — | 2001-03-13 |
| 6187092 | Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process | — | 2001-02-13 |
| 6188306 | On-chip transformers | — | 2001-02-13 |
| 6163052 | Trench-gated vertical combination JFET and MOSFET devices | Yowjuang W. Liu | 2000-12-19 |
| 6150693 | Short channel non-self aligned VMOS field effect transistor | — | 2000-11-21 |
| 6146985 | Low capacitance interconnection | — | 2000-11-14 |
| 6147378 | Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region | Yowjuang W. Liu | 2000-11-14 |
| 6140186 | Method of forming asymmetrically doped source/drain regions | Ming-Ren Lin, Peng Fang | 2000-10-31 |
| 6124608 | Non-volatile trench semiconductor device having a shallow drain region | Yowjuang W. Liu, Yu Sun | 2000-09-26 |