Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11693787 | Real time input/output address translation for virtualized systems | Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Fuoco, Jonathan Elliot Bergsagel +1 more | 2023-07-04 |
| 10949357 | Real time input/output address translation for virtualized systems | Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Fuoco, Jonathan Elliot Bergsagel +1 more | 2021-03-16 |
| 10817587 | Reconfigurable matrix multiplier system and method | Arthur John Redfern, Timothy David Anderson, Kai Chirca | 2020-10-27 |
| 10810281 | Outer product multipler system and method | Arthur John Redfern, Mihir Narendra Mody, Tarek Aziz Lahlou | 2020-10-20 |
| 10649786 | Reduced stack usage in a multithreaded processor | — | 2020-05-12 |
| 10114638 | Command message generation and execution using a machine code-instruction | — | 2018-10-30 |
| 9798674 | N-ary tree for mapping a virtual memory space | — | 2017-10-24 |
| 9519588 | Bounded cache searches | — | 2016-12-13 |
| 9367470 | Bounded cache searches | — | 2016-06-14 |
| 9256548 | Rule-based virtual address translation for accessing data | Marvin W. Martinez, Jr., John H. W. Bettink, John C. Carney, Mark W. Hervin | 2016-02-09 |
| 9176739 | System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions | — | 2015-11-03 |
| 8245014 | Thread interleaving in a multithreaded embedded processor | Earl T. Cohen, John J. Williams, Jr. | 2012-08-14 |
| 8156309 | Translation look-aside buffer with variable page sizes | — | 2012-04-10 |
| 7739426 | Descriptor transfer logic | Christopher E. White, Jonathan Rosen, John Andrew Fingerhut, Barry S. Burns | 2010-06-15 |
| 7664897 | Method and apparatus for communicating over a resource interconnect | Earl T. Cohen, William N. Eatherton, John J. Williams, Jr., John Andrew Fingerhut | 2010-02-16 |
| 7551617 | Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor | Will Eatherton, Earl T. Cohen, John Andrew Fingerhut, John J. Williams, Jr. | 2009-06-23 |
| 7441101 | Thread-aware instruction fetching in a multithreaded embedded processor | Earl T. Cohen, John J. Williams, Jr. | 2008-10-21 |
| 7360064 | Thread interleaving in a multithreaded embedded processor | Earl T. Cohen, John J. Williams, Jr. | 2008-04-15 |
| 7206922 | Instruction memory hierarchy for an embedded processor | — | 2007-04-17 |
| 6895494 | Sub-pipelined and pipelined execution in a VLIW | Laurence R. Simar | 2005-05-17 |
| 6895493 | System and method for processing data in an integrated circuit environment | Zheng Zhu | 2005-05-17 |
| 6781411 | Flip flop with reduced leakage current | Clive Bittlestone, Peter Cumming, Christopher Michael Barr | 2004-08-24 |
| 6766440 | Microprocessor with conditional cross path stall to minimize CPU cycle time length | David Hoyle | 2004-07-20 |
| 6571363 | Single event upset tolerant microprocessor architecture | — | 2003-05-27 |
| 6567906 | Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory | Frank L. Laczko, Sr. | 2003-05-20 |