Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11373720 | Analog memory cells with valid flag | Peter Robert Linder, Erik James Welsh, Gene A. Frantz | 2022-06-28 |
| 11347478 | Analog arithmetic unit | Erik James Welsh, Peter Robert Linder, Gene A. Frantz | 2022-05-31 |
| 11171651 | Mixed signal computer | Erik James Welsh, Peter Robert Linder, Gene A. Frantz | 2021-11-09 |
| 7886255 | Method for design of programmable data processors | Reid E. Tatge | 2011-02-08 |
| 7039790 | Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit | Richard A. Brown | 2006-05-02 |
| 6895494 | Sub-pipelined and pipelined execution in a VLIW | Donald E. Steiss | 2005-05-17 |
| 6625719 | Processing devices with improved addressing capabilities systems and methods | Jerald G. Leach, Alan L. Davis, Reid E. Tatge | 2003-09-23 |
| 6411984 | Processor integrated circuit | Jerald G. Leach, Alan L. Davis, Reid E. Tatge | 2002-06-25 |
| 6374346 | Processor with conditional execution of every instruction | Natarajan Seshan, Reid E. Tatge, Alan L. Davis | 2002-04-16 |
| 6182203 | Microprocessor | Richard H. Scales, Natarajan Seshan | 2001-01-30 |
| 6055628 | Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks | Natarajan Seshan | 2000-04-25 |
| 5964825 | Manipulation of boolean values and conditional operation in a microprocessor | Nat Seshan | 1999-10-12 |
| 5841379 | Method and apparatus for selectively counting consecutive bits | Natarajan Seshan | 1998-11-24 |
| 5826101 | Data processing device having split-mode DMA channel | Michael D. Beck | 1998-10-20 |
| 5809309 | Processing devices with look-ahead instruction systems and methods | Jerald G. Leach | 1998-09-15 |
| 5751991 | Processing devices with improved addressing capabilities, systems and methods | Jerald G. Leach, Alan L. Davis, Reid E. Tatge | 1998-05-12 |
| 5594914 | Method and apparatus for accessing multiple memory devices | Joseph A. Coomes, Steve Marshall | 1997-01-14 |
| 5535348 | Block instruction | Jerald G. Leach, Joseph A. Coomes, Steve Marshall | 1996-07-09 |
| 5511146 | Excitory and inhibitory cellular automata for computational networks | — | 1996-04-23 |
| 5410652 | Data communication control by arbitrating for a data transfer control token with facilities for halting a data transfer by maintaining possession of the token | Jerald G. Leach | 1995-04-25 |
| 5390304 | Method and apparatus for processing block instructions in a data processor | Jerald G. Leach | 1995-02-14 |
| 5305446 | Processing devices with improved addressing capabilities, systems and methods | Jerald G. Leach, Alan L. Davis, Reid E. Tatge | 1994-04-19 |