Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417380 | Machine learning accelerator mechanism | Amit Bleiweiss, Anavai Ramesh, Asit K. Mishra, Jeffrey J. Cook, Srinivas Sridharan +8 more | 2025-09-16 |
| 12380326 | Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism | Eriko Nurvitadhi, Amit Bleiweiss, Eugene Wang, Saritha Dwarakapuram, Sabareesh Ganapathy | 2025-08-05 |
| 12135981 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2024-11-05 |
| 12039435 | Machine learning accelerator mechanism | Amit Bleiweiss, Anavai Ramesh, Asit K. Mishra, Jeffrey J. Cook, Srinivas Sridharan +8 more | 2024-07-16 |
| 12014265 | Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism | Eriko Nurvitadhi, Amit Bleiweiss, Eugene Wang, Saritha Dwarakapuram, Sabareesh Ganapathy | 2024-06-18 |
| 11693691 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2023-07-04 |
| 11636327 | Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism | Eriko Nurvitadhi, Amit Bleiweiss, Eugene Wang, Saritha Dwarakapuram, Sabareesh Ganapathy | 2023-04-25 |
| 11416248 | Method and system for efficient floating-point compression | Jaewoong Sim, Alaa R. Alameldeen, Eriko Nurvitadhi | 2022-08-16 |
| 11416281 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2022-08-16 |
| 11373088 | Machine learning accelerator mechanism | Amit Bleiweiss, Anavai Ramesh, Asit K. Mishra, Jeffrey J. Cook, Srinivas Sridharan +8 more | 2022-06-28 |
| 11328037 | Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers | Jack Z. Yinger, Andrew Chaang Ling, Tomasz Czajkowski, Davor Capalija, Eriko Nurvitadhi | 2022-05-10 |
| 11216722 | Hardware accelerator template and design framework for implementing recurrent neural networks | Eriko Nurvitadhi | 2022-01-04 |
| 11113053 | Data element comparison processors, methods, systems, and instructions | Asit K. Mishra, Edward T. Grochowski, Jonathan Pearce, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more | 2021-09-07 |
| 11093277 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2021-08-17 |
| 10915328 | Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency | Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey J. Cook | 2021-02-09 |
| 10831505 | Architecture and method for data parallel single program multiple data (SPMD) execution | Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey J. Cook, Abhijit Davare +1 more | 2020-11-10 |
| 10776110 | Apparatus and method for adaptable and efficient lane-wise tensor processing | Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey J. Cook, Abhijit Davare +6 more | 2020-09-15 |
| 10740281 | Asymmetric performance multicore architecture with same instruction set architecture | Varghese George, Sanjeev Jahagirdar | 2020-08-11 |
| 10635448 | Byte and nibble sort instructions that produce sorted destination register and destination index mapping | Asit K. Mishra, Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall | 2020-04-28 |
| 10489063 | Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication | Asit K. Mishra, Edward T. Grochowski | 2019-11-26 |
| 10452551 | Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register | Ganesh Venkatesh, Christopher B. Wilkerson, Seth H. Pugsley | 2019-10-22 |
| 10437562 | Apparatus and method for processing sparse data | Eriko Nurvitadhi, Yu Wang | 2019-10-08 |
| 10423411 | Data element comparison processors, methods, systems, and instructions | Asit K. Mishra, Edward T. Grochowski, Jonathan Pearce, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more | 2019-09-24 |
| 10409613 | Processing devices to perform a key value lookup instruction | Asit K. Mishra, Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall | 2019-09-10 |
| 10387037 | Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies | Ganesh Venkatesh | 2019-08-20 |