Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10642744 | Memory type which is cacheable yet inaccessible by speculative instructions | Darrell D. Boggs, Ross Segelken, Mike Cornaby, Nick Fortino, Shailender Chaudhry +3 more | 2020-05-05 |
| 10409763 | Apparatus and method for efficiently implementing a processor pipeline | Patrick P. Lai, Ethan Schuchman, David Keppel, Polychronis Xekalakis, Joshua B. Fryman +7 more | 2019-09-10 |
| 10338927 | Method and apparatus for implementing a dynamic out-of-order processor pipeline | Naveen Neelakantam, John H. Kelm, Polychronis Xekalakis | 2019-07-02 |
| 10061587 | Instruction and logic for bulk register reclamation | David Keppel, Fernando Latorre, Marc Lupon, Grigorios Magklis, Naveen Neelakantam +2 more | 2018-08-28 |
| 9823925 | Instruction and logic for a logical move in an out-of-order processor | Rupert Brauch, Raul Martinez, Naveen Neelakantam, Thang Vu | 2017-11-21 |
| 9612840 | Method and apparatus for implementing a dynamic out-of-order processor pipeline | Naveen Neelakantam, John H. Kelm, Polychronis Xekalakis | 2017-04-04 |
| 9569212 | Instruction and logic for a memory ordering buffer | John H. Kelm, Naveen Neelakantam | 2017-02-14 |
| 9342303 | Modified execution using context sensitive auxiliary code | James E. Smith, Shiliang Hu, Youfeng Wu | 2016-05-17 |
| 9256497 | Checkpoints associated with an out of order architecture | John H. Kelm, Naveen Neelakantam | 2016-02-09 |