Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9536030 | Optimization of integrated circuit physical design | Niels Fricke, Karsten Muuss, Peter Verwegen | 2017-01-03 |
| 8959275 | Byte selection and steering logic for combined byte shift and byte permute vector unit | Markus Kaltenbach, Jens Leenstra, Philipp Panitz | 2015-02-17 |
| 8959276 | Byte selection and steering logic for combined byte shift and byte permute vector unit | Markus Kaltenbach, Jens Leenstra, Philipp Panitz | 2015-02-17 |
| 8560983 | Incorporating synthesized netlists as subcomponents in a hierarchical custom design | Uwe Brandt, Thomas Makowski, Holger Wetter | 2013-10-15 |
| 8086657 | Adder structure with midcycle latch for power reduction | Wilhelm Haller, Rolf Sautter, Ulrich Weiss | 2011-12-27 |
| 7406495 | Adder structure with midcycle latch for power reduction | Wilhelm Haller, Rolf Sautter, Ulrich Weiss | 2008-07-29 |
| 7095252 | Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates | Michael A. Haase, Wilhelm Haller, Rolf Sautter | 2006-08-22 |
| 5870324 | Contents-addressable memory | Klaus Helwig | 1999-02-09 |