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Method of forming phase change memory devices in a pulsed DC deposition chamber |
Roger Hamamjy, Kuo-Wei Chang, Sean Lee |
2011-02-15 |
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Epitaxial CoSi2 on MOS devices |
Chan Soo Shin, Ivan Petrov, Joseph Greene |
2005-01-25 |
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Method for forming an epitaxial cobalt silicide layer on MOS devices |
Chan Soo Shin, Daniel Leo Gall, Ivan Petrov, Joseph Greene |
2004-09-28 |
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Method for large-scale fabrication of atomic-scale structures on material surfaces using surface vacancies |
Kenji Ohmori, Ivan Petrov, Joseph Greene |
2004-07-13 |
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Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low |
2002-02-26 |
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Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low |
2001-10-02 |
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Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication |
Eng Hua Lim, Kin Leong Pey, Soh Yun Siah, Chun Hui Low |
2001-08-07 |
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Partially recessed shallow trench isolation method for fabricating borderless contacts |
Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low |
2001-07-24 |
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Method to form shallow trench isolations with rounded corners and reduced trench oxide recess |
Soh Yun Siah, Eng Hua Lim, Kong Hean Lee, Chun Hui Low |
2001-05-08 |
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Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device |
Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Pei Ching Lee |
2000-12-26 |
| 6093628 |
Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application |
Kin Leong Pey, Soh Yun Siah, Eng Hwa Lim, Lap Chan |
2000-07-25 |