Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8283713 | Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics | John G. Jansen, Ce Chen, Shahriar Moinian | 2012-10-09 |
| 5719084 | Method for the controlled formation of voids in doped glass dielectric films | Thomas G. Mallon, Wei-Jen Hsia, Atsushi Shimoda | 1998-02-17 |
| 5717238 | Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device | Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi R. Padmanabhan, Douglas T. Grider | 1998-02-10 |
| 5585286 | Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device | Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi R. Padmanabhan, Douglas T. Grider | 1996-12-17 |
| 5278103 | Method for the controlled formation of voids in doped glass dielectric films | Thomas G. Mallon, Wei-Jen Hsia, Atsushi Shimoda | 1994-01-11 |