Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490265 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2019-11-26 |
| 10482952 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2019-11-19 |
| 9672901 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2017-06-06 |
| 9343139 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2016-05-17 |
| 9129708 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2015-09-08 |
| 8848463 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2014-09-30 |
| 8625368 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2014-01-07 |
| 8553488 | Performing stuck-at testing using multiple isolation circuits | Daniel C. Murray, Conrad H. Ziesler | 2013-10-08 |
| 8476930 | Level shifter with embedded logic and low minimum voltage | Vincent R. von Kaenel, Naveen Javarappa, Greg M. Hess | 2013-07-02 |
| 8416635 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2013-04-09 |
| 8395954 | Leakage and NBTI reduction technique for memory | Greg M. Hess, Hang Huang | 2013-03-12 |
| 8341578 | Clock gater with test features and low setup time | Shaishav Desai, Edgardo F. Klass, Pradeep Trivedi, Sridhar Narayanan | 2012-12-25 |
| 8286987 | Animated novelty device | Daniel J. Chesnicka, Mark J. McIntyre | 2012-10-16 |
| 8289785 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2012-10-16 |
| 8219755 | Fast hit override | — | 2012-07-10 |
| 8203898 | Leakage and NBTI reduction technique for memory | Greg M. Hess, Hang Huang | 2012-06-19 |
| 8171326 | L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down | James B. Keller, Tse-Yu Yeh, Ramesh Gunna | 2012-05-01 |
| 8102728 | Cache optimizations using multiple threshold voltage transistors | Greg M. Hess, Hang Huang | 2012-01-24 |
| 8098534 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage | Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam | 2012-01-17 |
| 8091915 | Animated novelty device | Daniel J. Chesnicka, Mark J. McIntyre | 2012-01-10 |
| 8015356 | Fast hit override | — | 2011-09-06 |
| 7995410 | Leakage and NBTI reduction technique for memory | Greg M. Hess, Hang Huang | 2011-08-09 |
| 7994820 | Level shifter with embedded logic and low minimum voltage | Vincent R. von Kaenel, Naveen Javarappa, Greg M. Hess | 2011-08-09 |
| 7915920 | Low latency, power-down safe level shifter | Vincent R. von Kaenel | 2011-03-29 |
| 7834662 | Level shifter with embedded logic and low minimum voltage | Vincent R. von Kaenel, Naveen Javarappa, Greg M. Hess | 2010-11-16 |