AJ

Alan S. Krech, Jr.

HP HP: 24 patents #48 of 7,018Top 1%
AT Agilent Technologies: 16 patents #80 of 3,411Top 3%
AD Advantest: 9 patents #102 of 1,193Top 9%
VP Verigy Pte.: 1 patents #2 of 22Top 10%
VP Verigy (Singapore) Pte.: 1 patents #55 of 115Top 50%
📍 Fort Collins, CO: #40 of 3,421 inventorsTop 2%
🗺 Colorado: #396 of 40,980 inventorsTop 1%
Overall (All Time): #52,232 of 4,157,543Top 2%
51
Patents All Time

Issued Patents All Time

Showing 1–25 of 51 patents

Patent #TitleCo-InventorsDate
11913990 Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors Olaf PÖPPE, Klaus-Dieter Hilliges 2024-02-27
11415628 Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program using a buffer memory Olaf PÖPPE, Klaus-Dieter Hilliges 2022-08-16
10948540 Integrated protocol analyzer configured within automated test equipment (ate) hardware Jesse Hobbs, Kazuya Aramaki, Donald V. Organ, Jeffrey F. Stone 2021-03-16
10693568 Adapting serdes receivers to a UFS receiver protocol Sivanarayana Pandian Rajadurai, Preet Paul Singh, Darrin Paul Albers 2020-06-23
10652131 Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array Michael Jones, Eric Barr Kushnick 2020-05-12
9842038 Method and system for advanced fail data transfer mechanisms Xinguo Zhang, Yi LIU, Ze'ev Raz, Darrin Paul Albers, Shigeo Chiyoda +1 more 2017-12-12
9612272 Testing memory devices with parallel processing operations Xinguo Zhang, Michael Jones, Ken Hanh Duc Lai, Edmundo De La Puente 2017-04-04
9281080 Staged buffer caching in a system for testing a device under test Michael Jones, Edmundo DeLaPuente 2016-03-08
9267965 Flexible test site synchronization Michael Jones, Takahiro Yasui, Edmundo DeLaPuente, Taichi Fukuda 2016-02-23
7404122 Mapping logic for loading control of crossbar multiplexer select RAM 2008-07-22
7339844 Memory device fail summary data reduction for improved redundancy analysis Stephen D Jordan, John M Freeseman 2008-03-04
7181660 Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test Stephen D Jordan, Hsiu-Huan Shen 2007-02-20
7076714 Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors John Howard Cook, III, Stephen D Jordan, Edmundo De La Puente, John M Freesman 2006-07-11
6973404 Method and apparatus for administering inversion property in a memory tester John M Freeseman 2005-12-06
6968545 Method and apparatus for no-latency conditional branching Stephen D Jordan 2005-11-22
6834364 Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences Brad D. Reak, Randy L. Bailey, John M Freeseman 2004-12-21
6833695 Simultaneous display of data gathered using multiple data gathering mechanisms Hsui-Huan Shen, Stephen D Jordan 2004-12-21
6781584 Recapture of a portion of a displayed waveform without loss of existing data in the waveform display Hsiu-Huan Shen, Stephen D Jordan 2004-08-24
6779140 Algorithmically programmable memory tester with test sites operating in a slave mode Edmundo De La Puente, Joel Buck-Gengler 2004-08-17
6763490 Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester John M Freeseman 2004-07-13
6748562 Memory tester omits programming of addresses in detected bad columns John M Freeseman, Ken Hanh Duc Lai 2004-06-08
6687855 Apparatus and method for storing information during a test program John M Freeseman 2004-02-03
6671844 Memory tester tests multiple DUT's per test site John M Freeseman, Randy L. Bailey, Edmundo De La Puente 2003-12-30
6598112 Method and apparatus for executing a program using primary, secondary and tertiary memories Stephen D Jordan 2003-07-22
6591385 Method and apparatus for inserting programmable latency between address and data information in a memory tester John M Freeseman 2003-07-08