Issued Patents All Time
Showing 101–125 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6928635 | Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits | Michael Sanie | 2005-08-09 |
| 6414542 | Integrated circuit with relative sense inversion of signals along adjacent parallel signal paths | Xi-Wei Lin | 2002-07-02 |
| 6316834 | Tungsten plugs for integrated circuits and method for making same | Calvin T. Gabriel, Xi-Wei Lin | 2001-11-13 |
| 6313542 | Method and apparatus for detecting edges under an opaque layer | Kouros Ghandehari, Satyendra Sethi, Daniel C. Baker | 2001-11-06 |
| 6229685 | Thin capacitive structures and methods for making the same | Subhas Bothra, Calvin T. Gabriel | 2001-05-08 |
| 6176983 | Methods of forming a semiconductor device | Subhas Bothra, Samit Sengupta | 2001-01-23 |
| RE36893 | Anti-fuse structure for reducing contamination of the anti-fuse material | Subhash R. Nariani | 2000-10-03 |
| 5990561 | Tungsten plugs for integrated circuits and methods for making same | Calvin T. Gabriel, Xi-Wei Lin | 1999-11-23 |
| 5852497 | Method and apparatus for detecting edges under an opaque layer | Kouros Ghandehari, Satyendra Sethi, Daniel C. Baker | 1998-12-22 |
| 5834356 | Method of making high resistive structures in salicided process semiconductor devices | Subhas Bothra, Xi-Wei Lin | 1998-11-10 |
| 5811346 | Silicon corner rounding in shallow trench isolation process | Harlan Lee Sur, Jr., Olivier Laparra | 1998-09-22 |
| 5804502 | Tungsten plugs for integrated circuits and methods for making same | Calvin T. Gabriel, Xi-Wei Lin | 1998-09-08 |
| 5763937 | Device reliability of MOS devices using silicon rich plasma oxide films | Vivek Jain, Subhash R. Nariani, Kuang-Yeh Chang | 1998-06-09 |
| 5602056 | Method for forming reliable MOS devices using silicon rich plasma oxide film | Vivek Jain, Subhash R. Nariani, Kuang-Yeh Chang | 1997-02-11 |
| 5573970 | Method for reducing contamination of anti-fuse material in an anti-fuse structure | Subhash R. Nariani | 1996-11-12 |
| 5522957 | Method for leak detection in etching chambers | Milind Weling, Calvin T. Gabriel, Vivek Jain | 1996-06-04 |
| 5496774 | Method improving integrated circuit planarization during etchback | Vivek Jain, Milind Weling | 1996-03-05 |
| 5492865 | Method of making structure for suppression of field inversion caused by charge build-up in the dielectric | Subhash R. Nariani, Vivek Jain, Kuang-Yeh Chang | 1996-02-20 |
| 5493146 | Anti-fuse structure for reducing contamination of the anti-fuse material | Subhash R. Nariani | 1996-02-20 |
| 5436410 | Method and structure for suppressing stress-induced defects in integrated circuit conductive lines | Vivek Jain | 1995-07-25 |
| 5403780 | Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device | Vivek Jain, Milind G. Weiling | 1995-04-04 |
| 5399533 | Method improving integrated circuit planarization during etchback | Vivek Jain, Milind Weling | 1995-03-21 |
| 5374833 | Structure for suppression of field inversion caused by charge build-up in the dielectric | Subhash R. Nariani, Vivek Jain, Kuang-Yeh Chang | 1994-12-20 |
| 5332868 | Method and structure for suppressing stress-induced defects in integrated circuit conductive lines | Vivek Jain | 1994-07-26 |
| 5290727 | Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors | Vivek Jain, Subhash R. Nariani | 1994-03-01 |