Issued Patents All Time
Showing 76–100 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8466005 | Method for forming metal oxides and silicides in a memory device | Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi | 2013-06-18 |
| 8466446 | Atomic layer deposition of metal oxide materials for memory applications | Yun Wang, Vidyut Gopal, Imran Hashim, Tony Chiag | 2013-06-18 |
| 8426270 | Memory device with a textured lowered electrode | — | 2013-04-23 |
| 8413096 | Analysis of stress impact on transistor performance | Victor Moroz | 2013-04-02 |
| 8407634 | Analysis of stress impact on transistor performance | Victor Moroz | 2013-03-26 |
| 8347252 | Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array | Victor Moroz | 2013-01-01 |
| 8288297 | Atomic layer deposition of metal oxide materials for memory applications | Yun Wang, Vidyut Gopal, Imran Hashim, Tony Chiag | 2012-10-16 |
| 8219961 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Victor Moroz, Kishore Singhal, Xi-Wei Lin | 2012-07-10 |
| 8086990 | Method of correlating silicon stress to device instance parameters for circuit simulation | Xi-Wei Lin, Victor Moroz | 2011-12-27 |
| 8069430 | Stress-managed revision of integrated circuit layouts | Victor Moroz, Xi-Wei Lin | 2011-11-29 |
| 8035168 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Xi-Wei Lin | 2011-10-11 |
| 7949985 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Victor Moroz, Kishore Singhal, Xi-Wei Lin | 2011-05-24 |
| 7897479 | Managing integrated circuit stress using dummy diffusion regions | Xi-Wei Lin, Victor Moroz | 2011-03-01 |
| 7895548 | Filler cells for design optimization in a place-and-route system | Xi-Wei Lin, Jyh Chwen Frank Lee | 2011-02-22 |
| 7863146 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Xi-Wei Lin | 2011-01-04 |
| 7767515 | Managing integrated circuit stress using stress adjustment trenches | Victor Moroz, Xi-Wei Lin | 2010-08-03 |
| 7739095 | Method for determining best and worst cases for interconnects in timing analysis | Xi-Wei Lin | 2010-06-15 |
| 7705406 | Transistor array with selected subset having suppressed layout sensitivity of threshold voltage | Victor Moroz | 2010-04-27 |
| 7691693 | Method for suppressing layout sensitivity of threshold voltage in a transistor array | Victor Moroz | 2010-04-06 |
| 7600207 | Stress-managed revision of integrated circuit layouts | Victor Moroz, Xi-Wei Lin | 2009-10-06 |
| 7584438 | Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array | Victor Moroz | 2009-09-01 |
| 7542891 | Method of correlating silicon stress to device instance parameters for circuit simulation | Xi-Wei Lin, Victor Moroz | 2009-06-02 |
| 7543254 | Method and apparatus for fast identification of high stress regions in integrated circuit structure | Xiaopeng Xu | 2009-06-02 |
| 7484198 | Managing integrated circuit stress using dummy diffusion regions | Xi-Wei Lin, Victor Moroz | 2009-01-27 |
| 6931617 | Mask cost driven logic optimization and synthesis | Michael Sanie, Susan Jennifer Lippincott | 2005-08-16 |