Issued Patents All Time
Showing 26–50 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9715388 | Instruction and logic to monitor loop trip count and remove loop optimizations | Jaewoong Chung, Hyunchul Park, Hongbo Rong, Cheng Wang | 2017-07-25 |
| 9715376 | Energy/performance with optimal communication in dynamic parallelization of single threaded programs | Cheng Wang | 2017-07-25 |
| 9710280 | Overlapping atomic regions in a processor | Jaewoong Chung, Cheng Wang | 2017-07-18 |
| 9710391 | Methods and apparatuses for efficient load processing using buffers | Wei Liu, Christopher B. Wilkerson, Herbert Hum | 2017-07-18 |
| 9710279 | Method and apparatus for speculative vectorization | Nalini Vasudevan, Cheng Wang, Albert Hartono, Sara S. Baghsorkhi | 2017-07-18 |
| 9697040 | Software replayer for transactional memory programs | Justin E. Gottschlich, Gilles A. Pokam, Shiliang Hu, Rolf Kassa, Irina Calciu | 2017-07-04 |
| 9690582 | Instruction and logic for cache-based speculative vectorization | Nalini Vasudevan, Cheng Wang, Sara S. Baghsorkhi, Albert Hartono | 2017-06-27 |
| 9690552 | Technologies for low-level composable high performance computing libraries | Hongbo Rong, Peng Tu, Tatiana Shpeisman, Hai Paul Liu, Todd Alan Anderson +5 more | 2017-06-27 |
| 9672019 | Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads | David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman +10 more | 2017-06-06 |
| 9588814 | Fast approximate conflict detection | Sara S. Baghsorkhi, Albert Hartono, Cheng Wang | 2017-03-07 |
| 9542211 | Co-designed dynamic language accelerator for a processor | Cheng Wang, Hongbo Rong, Hyunchul Park | 2017-01-10 |
| 9519467 | Efficient and consistent software transactional memory | Cheng Wang, Wei-Yu Chen, Bratin Saha, Ali-Reza Adl-Tabatabai | 2016-12-13 |
| 9501135 | Dynamic core selection for heterogeneous multi-core systems | Shiliang Hu, Edson Borin, Cheng Wang | 2016-11-22 |
| 9495168 | Allocation of alias registers in a pipelined schedule | Hongbo Rong, Cheng Wang, Hyunchul Park | 2016-11-15 |
| 9405547 | Register allocation for rotation based alias protection register | Cheng Wang | 2016-08-02 |
| 9354882 | Methods and apparatus to manage partial-commit checkpoints with fixup support | Edson Borin | 2016-05-31 |
| 9342303 | Modified execution using context sensitive auxiliary code | James E. Smith, Denis M. Khartikov, Shiliang Hu | 2016-05-17 |
| 9292221 | Bi-directional copying of register content into shadow registers | Cheng Wang, Jaewoong Chung | 2016-03-22 |
| 9239712 | Software pipelining at runtime | Hongbo Rong, Hyunchul Park | 2016-01-19 |
| 9223714 | Instruction boundary prediction for variable length instruction set | Mauricio Breternitz, Peter G. Sassone, James Mason, Aashish Phansalkar, Balaji Vijayan | 2015-12-29 |
| 9170792 | Dynamic optimization of pipelined software | Hyunchul Park, Hongbo Rong | 2015-10-27 |
| 9152417 | Expediting execution time memory aliasing checking | Cheng Wang | 2015-10-06 |
| 9146844 | Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region | Mauricio Breternitz, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles | 2015-09-29 |
| 9135139 | Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions | Justin E. Gottschlich, Gilles A. Pokam, Shiliang Hu, Ali-Reza Adl-Tabatabai, Cristiano L. Pereira | 2015-09-15 |
| 9117021 | Methods and apparatus to manage concurrent predicate expressions | Justin E. Gottschlich, Cristiano L. Pereira, Gilles A. Pokam | 2015-08-25 |