Issued Patents All Time
Showing 51–75 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8954775 | Power gating functional units of a processor | Jaewoong Chung, Hanjun Kim | 2015-02-10 |
| 8935678 | Methods and apparatus to form a resilient objective instruction construct | Cheng Wang, Ho-Seop Kim | 2015-01-13 |
| 8789031 | Software constructed strands for execution on a multi-core architecture | Wei Liu, Lixin Su, Herbert Hum | 2014-07-22 |
| 8683243 | Dynamic core selection for heterogeneous multi-core systems | Shiliang Hu, Edson Borin, Cheng Wang | 2014-03-25 |
| 8549267 | Methods and apparatus to manage partial-commit checkpoints with fixup support | Edson Borin | 2013-10-01 |
| 8549504 | Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region | Mauricio Breternitz, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles | 2013-10-01 |
| 8522223 | Automatic function call in multithreaded application | Cheng Wang, Wei-Yu Chen, Zhiwei Ying | 2013-08-27 |
| 8452946 | Methods and apparatuses for efficient load processing using buffers | Wei Liu, Christopher B. Wilkerson, Herbert Hum | 2013-05-28 |
| 8443343 | Context-sensitive slicing for dynamically parallelizing binary programs | Joseph Blomstedt, Cheng Wang | 2013-05-14 |
| 8433852 | Method and apparatus for fuzzy stride prefetch | Shiliang Hu | 2013-04-30 |
| 8418156 | Two-stage commit (TSC) region for dynamic binary optimization in X86 | Cheng Wang | 2013-04-09 |
| 8332558 | Compact trace trees for dynamic binary parallelization | Joao Paulo Porto, Edson Borin, Cheng Wang | 2012-12-11 |
| 8321840 | Software flow tracking using multiple threads | Vijayanand Nagarajan, Ho-Seop Kim, Rajiv Gupta | 2012-11-27 |
| 8316360 | Methods and apparatus to optimize the parallel execution of software processes | Byoungro So, Anwar Ghuloum | 2012-11-20 |
| 8296749 | Program translation and transactional memory formation | Chengyan Zhao, Cheng Wang | 2012-10-23 |
| 8156480 | Methods and apparatus to form a resilient objective instruction construct | Cheng Wang, Ho-Seop Kim | 2012-04-10 |
| 8146106 | On-demand emulation via user-level exception handling | Ho-Seop Kim, Mauricio Breternitz | 2012-03-27 |
| 8132158 | Mechanism for software transactional memory commit/abort in unmanaged runtime environment | Cheng Wang, Bratin Saha, Ali-Reza Adl-Tabatabai | 2012-03-06 |
| 8099587 | Compressing and accessing a microcode ROM | Sangwook Kim, Mauricio Breternitz, Herbert Hum | 2012-01-17 |
| 8060482 | Efficient and consistent software transactional memory | Cheng Wang, Wei-Yu Chen, Bratin Saha, Ali-Reza Adl-Tabatabai | 2011-11-15 |
| 8001421 | Compiler technique for efficient register checkpointing to support transaction roll-back | Cheng Wang | 2011-08-16 |
| 7937620 | Transient fault detection by integrating an SRMT code and a non SRMT code in a single application | Cheng Wang | 2011-05-03 |
| 7937621 | Transient fault detection by integrating an SRMT code and a non SRMT code in a single application | Cheng Wang | 2011-05-03 |
| 7865885 | Using transactional memory for precise exception handling in aggressive dynamic binary optimizations | Cheng Wang, Ho-Seop Kim | 2011-01-04 |
| 7844946 | Methods and apparatus to form a transactional objective instruction construct from lock-based critical sections | Cheng Wang | 2010-11-30 |