AH

Albert Hartono

IN Intel: 17 patents #2,418 of 30,777Top 8%
Overall (All Time): #274,701 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10402177 Methods and systems to vectorize scalar computer program loops having loop-carried dependences Jayashankar Bharadwaj, Nalini Vasudevan, Sara S. Baghsorkhi 2019-09-03
10372450 Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Sara S. Baghsorkhi +1 more 2019-08-06
10324768 Lightweight restricted transactional memory for speculative compiler optimization Cheng Wang, Youfeng Wu, Sara S. Baghsorkhi, Robert Valentine 2019-06-18
9921832 Instruction to reduce elements in a vector register with strided access pattern Jayashankar Bharadwaj, Nalini Vasudevan, Sara S. Baghsorkhi, Victor W. Lee, Daehyun Kim 2018-03-20
9910650 Method and apparatus for approximating detection of overlaps between memory ranges Nalini Vasudevan, Sara S. Baghsorkhi, Cheng Wang, Youfeng Wu 2018-03-06
9898266 Loop vectorization methods and apparatus Nalini Vasudevan, Jayashankar Bharadwaj, Christopher J. Hughes, Milind B. Girkar, Mark J. Charney +4 more 2018-02-20
9798541 Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register Jayashankar Bharadwaj, Nalini Vasudevan, Victor W. Lee, Daehyun Kim, Sara S. Baghsorkhi 2017-10-24
9733913 Methods and systems to vectorize scalar computer program loops having loop-carried dependences Jayashankar Bharadwaj, Nalini Vasudevan, Sara S. Baghsorkhi 2017-08-15
9720667 Automatic loop vectorization using hardware transactional memory Sara S. Baghsorkhi, Youfeng Wu, Nalini Vasudevan, Cheng Wang 2017-08-01
9710279 Method and apparatus for speculative vectorization Nalini Vasudevan, Cheng Wang, Youfeng Wu, Sara S. Baghsorkhi 2017-07-18
9703558 Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Sara S. Baghsorkhi +1 more 2017-07-11
9690582 Instruction and logic for cache-based speculative vectorization Nalini Vasudevan, Youfeng Wu, Cheng Wang, Sara S. Baghsorkhi 2017-06-27
9588814 Fast approximate conflict detection Sara S. Baghsorkhi, Youfeng Wu, Cheng Wang 2017-03-07
9268626 Apparatus and method for vectorization with speculation support Jayashankar Bharadwaj, Victor W. Lee, Kim Daehyun, Nalini Vasudevan, Tin-Fook Ngai +1 more 2016-02-23
9268541 Methods and systems to vectorize scalar computer program loops having loop-carried dependences Jayashankar Bharadwaj, Nalini Vasudevan, Sara S. Baghsorkhi 2016-02-23
9244677 Loop vectorization methods and apparatus Nalini Vasudevan, Jayashankar Bharadwaj, Christopher J. Hughes, Milind B. Girkar, Mark J. Charney +4 more 2016-01-26
9189236 Speculative non-faulting loads and gathers Jayashankar Bharadwaj, Nalini Vasudevan, Victor W. Lee, Sara S. Baghsorkhi, Daehyun Kim 2015-11-17