Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8677298 | Programmable device configuration methods adapted to account for retiming | David Lewis, David Galloway, Ryan Fung | 2014-03-18 |
| 8661381 | Method and apparatus for performing optimization using Don't Care states | Shawn Malhotra | 2014-02-25 |
| 8645885 | Specification of multithreading in programmable device configuration | David Galloway, David Lewis | 2014-02-04 |
| 8588014 | Methods for memory interface calibration | Ryan Fung | 2013-11-19 |
| 8581624 | Integrated circuits with multi-stage logic regions | David Cashman, David Lewis | 2013-11-12 |
| 8578306 | Method and apparatus for performing asynchronous and synchronous reset removal during synthesis | — | 2013-11-05 |
| 8565033 | Methods for calibrating memory interface circuitry | Ivan Blunno, Ryan Fung, Navid Azizi | 2013-10-22 |
| 8510688 | Method and apparatus for performing multiple stage physical synthesis | Deshanand Singh, Gordon Raymond Chiu, Ivan Blunno, Stephen D. Brown | 2013-08-13 |
| 8296696 | Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis | Gordon Raymond Chiu, Deshanand Singh, Ivan Blunno, Stephen D. Brown | 2012-10-23 |
| 8201114 | Method and apparatus for performing look up table unpacking and repacking for resynthesis | Gordon Raymond Chiu, John Stuart Freeman | 2012-06-12 |
| 7996797 | Method and apparatus for performing multiple stage physical synthesis | Deshanand Singh, Gordon Raymond Chiu, Ivan Blunno, Stephen D. Brown | 2011-08-09 |
| 7797666 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories | Gordon Raymond Chiu, Deshanand Singh, Stephen D. Brown | 2010-09-14 |
| 7620925 | Method and apparatus for performing post-placement routability optimization | Gordon Raymond Chiu, Deshanand Singh, Stephen D. Brown | 2009-11-17 |
| 7594204 | Method and apparatus for performing layout-driven optimizations on field programmable gate arrays | Deshanand Singh, Paul McHardy, Chris G. Sanford, Gabriel Quan, Terry Borer +3 more | 2009-09-22 |
| 7565387 | Systems and methods for configuring a programmable logic device to perform a computation using carry chains | Chandra Shekar | 2009-07-21 |
| 7509597 | Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams | Deshanand Singh, Stephen D. Brown | 2009-03-24 |
| 7500216 | Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines | Ivan Blunno, Gordon Raymond Chiu, Deshanand Singh, Stephen D. Brown | 2009-03-03 |
| 7444613 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories | Gordon Raymond Chiu, Deshanand Singh, Stephen D. Brown | 2008-10-28 |
| 7412677 | Detecting reducible registers | Gordon Raymond Chiu, Deshanand Singh, Stephen D. Brown | 2008-08-12 |
| 7360190 | Method and apparatus for performing retiming on field programmable gate arrays | Deshanand Singh, Gabriel Quan, Terry Borer, Ian Chesal, Karl Schabas +1 more | 2008-04-15 |
| 7290239 | Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays | Deshanand Singh, Karl Schabas | 2007-10-30 |
| 7257800 | Method and apparatus for performing logic replication in field programmable gate arrays | Deshanand Singh, Gabriel Quan, Terry Borer, Paul McHardy, Ivan Hamer +2 more | 2007-08-14 |