Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8489660 | Digital random number generator using partially entropic data | Howard C. Herbert, George W. Cox, Shay Gueron, Jesse Walker, Charles E. Dike +7 more | 2013-07-16 |
| 8230203 | Detecting spin loops in a virtual machine environment | Gilbert Neiger, Randolph L. Campbell, James B. Crossland, Gideon Gerzon, Leena K. Puthiyedath +2 more | 2012-07-24 |
| 8171261 | Method and system for accessing memory in parallel computing using load fencing instructions | Salvador Palanca, Subramaniam Maiyuran, Shekoufeh Qawami | 2012-05-01 |
| 8145816 | System and method for deadlock free bus protection of resources during search execution | Douglas R. Moran, James A. Sutton | 2012-03-27 |
| 8131989 | Method and apparatus for establishing safe processor operating points | Varghese George, Sanjeev Jahagirdar, Stephen H. Gunther | 2012-03-06 |
| 7934076 | System and method for limiting exposure of hardware failure information for a secured execution environment | Shamanna M. Datta | 2011-04-26 |
| 7779239 | User opt-in processor feature control capability | Dion Rodgers, James A. Sutton | 2010-08-17 |
| 7664970 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, George Varghese, John B. Conrad, Robert Milstrey, Alon Navch +1 more | 2010-02-16 |
| 7370189 | Method and apparatus for establishing safe processor operating points in connection with a secure boot | Varghese George, Sanjeev Jahagirdar, Stephen H. Gunther | 2008-05-06 |
| 6898700 | Efficient saving and restoring state in task switching | William C. Alexander, Shreekant S. Thakkar, Patrice Roussel, Thomas R. Huff, Bryant Bigbee | 2005-05-24 |
| 6823353 | Method and apparatus for multiplying and accumulating complex numbers in a digital filter | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi | 2004-11-23 |
| 6678810 | MFENCE and LFENCE micro-architectural implementation method and system | Salvador Palanca, Subramaniam Maiyuran, Shekoufeh Qawami | 2004-01-13 |
| 6651151 | MFENCE and LFENCE micro-architectural implementation method and system | Salvador Palanca, Subramaniam Maiyuran, Shekoufeh Qawami | 2003-11-18 |
| 6546462 | CLFLUSH micro-architectural implementation method and system | Salvador Palanca, Subramaniam Maiyuran | 2003-04-08 |
| 6470370 | Method and apparatus for multiplying and accumulating complex numbers in a digital filter | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi | 2002-10-22 |
| 6289459 | Processor unique processor number feature with a user controllable disable capability | Shreekant S. Thakkar, Robert Sullivan, Frederick J. Pollack | 2001-09-11 |
| 6237016 | Method and apparatus for multiplying and accumulating data samples and complex coefficients | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi | 2001-05-22 |
| 6185671 | Checking data type of operands specified by an instruction using attributes in a tagged array architecture | Vladimir Pentovski, Gerald Bennett, Eric Heit, Glenn J. Hinton, Patrice Roussel | 2001-02-06 |
| 6058408 | Method and apparatus for multiplying and accumulating complex numbers in a digital filter | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi | 2000-05-02 |
| 5983253 | Computer system for performing complex digital filters | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi | 1999-11-09 |
| 5983257 | System for signal processing using multiply-add operations | Carole Dulong, Larry M. Mennemeier, Tuan Bui, Eiichi Kowashi, Alexander Peleg +3 more | 1999-11-09 |
| 5941964 | Bridge buffer management by bridge interception of synchronization events | Bruce A. Young, Jeff Rabe | 1999-08-24 |
| 5936872 | Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations | Larry M. Mennemeier, Alexander Peleg, Carole Dulong, Eiichi Kowashi | 1999-08-10 |
| 5887194 | Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked | Dave Carson, Bruce A. Young, Norman J. Rasmussen, Jeffrey L. Rabe | 1999-03-23 |
| 5852712 | Microprocessor having single poly-silicon EPROM memory for programmably controlling optional features | Michael J. Allen, Gregory K. Crain, Patrick P. Gelsinger, David Gray, Stuart T. Hopkins +7 more | 1998-12-22 |