Issued Patents All Time
Showing 26–50 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6895570 | System and method for optimizing routing lines in a programmable logic device | David Lewis, Vaughn Betz, Paul Leventis, Michael Chan, Cameron McClintock +3 more | 2005-05-17 |
| 6882177 | Tristate structures for programmable logic devices | Richard G. Cliff | 2005-04-19 |
| 6879183 | Programmable logic device architectures with super-regions having logic regions and a memory region | David Jefferson, Cameron McClintock, James Schleicher, Andy L. Lee, Manuel Mejia +3 more | 2005-04-12 |
| 6819135 | Fast signal conductor networks for programmable logic devices | Christopher F. Lane | 2004-11-16 |
| 6815981 | Programmable logic array integrated circuit devices | Richard G. Cliff, David Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane +7 more | 2004-11-09 |
| 6798242 | Programmable logic device with hierarchical interconnection resources | Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia, David Jefferson +2 more | 2004-09-28 |
| 6720796 | Multiple size memories in a programmable logic device | David Jefferson, Christopher F. Lane, Vikram Santurkar, Richard G. Cliff | 2004-04-13 |
| 6657456 | Programmable logic with on-chip DLL or PLL to distribute clock | David Jefferson, L. Todd Cope, Richard G. Cliff | 2003-12-02 |
| 6630842 | Routing architecture for a programmable logic device | David Lewis, Paul Leventis, Andy L. Lee, Brian Johnson, Richard G. Cliff +5 more | 2003-10-07 |
| 6605962 | PLD architecture for flexible placement of IP function blocks | Andy L. Lee, Cameron McClintock, Brian Johnson, Richard G. Cliff, Chris Lane +3 more | 2003-08-12 |
| 6577160 | Programmable logic device with hierarchical interconnection resources | Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia, David Jefferson +2 more | 2003-06-10 |
| 6480028 | Programmable logic device architectures with super-regions having logic regions and memory region | David Jefferson, Cameron McClintock, James Schleicher, Andy L. Lee, Manuel Mejia +3 more | 2002-11-12 |
| 6481000 | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits | Ketan Zaveri, Christopher F. Lane, Andy L. Lee, Cameron McClintock, Bruce B. Pedersen | 2002-11-12 |
| 6467017 | Programmable logic device having embedded dual-port random access memory configurable as single-port memory | Tony Ngai, Rakesh Patel, Richard G. Cliff | 2002-10-15 |
| 6462577 | Configurable memory structures in a programmable logic device | Andy L. Lee, Christopher F. Lane, Brian Johnson, Ketan Zaveri, Mario Guzman +1 more | 2002-10-08 |
| 6417694 | Programmable logic device with hierarchical interconnection resources | Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia, David Jefferson +2 more | 2002-07-09 |
| 6392438 | Programmable logic array integrated circuit devices | Richard G. Cliff, David Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane +7 more | 2002-05-21 |
| 6392954 | Dual port programmable logic device variable depth and width memory array | Christopher F. Lane, Manuel Mejia, Richard G. Cliff, Kerry Veenstra | 2002-05-21 |
| 6384630 | Techniques for programming programmable logic array devices | Richard G. Cliff, Kerry Veenstra, Andreas Papaliolios, Chiakang Sung, Richard Shaw Terrill +2 more | 2002-05-07 |
| 6373280 | Fast signal conductor networks for programmable logic devices | Christopher F. Lane | 2002-04-16 |
| 6366121 | Programmable logic array integrated circuit architectures | Richard G. Cliff, Francis B. Heile, Joseph Huang, Christopher F. Lane, Fung Fung Lee +7 more | 2002-04-02 |
| 6356110 | Multifunction memory array in a programmable logic device | Brian Johnson, Christopher F. Lane, Ketan Zaveri | 2002-03-12 |
| 6351152 | Look-up table using multi-level decode | Anil Gupta | 2002-02-26 |
| 6344755 | Programmable logic device with redundant circuitry | Manuel Mejia, Andy L. Lee, Bruce B. Pedersen | 2002-02-05 |
| 6337578 | Redundancy circuitry for programmable logic devices with interleaved input circuits | David Jefferson | 2002-01-08 |