Issued Patents All Time
Showing 76–100 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6037829 | Look-up table using multi-level decode | Anil Gupta | 2000-03-14 |
| 5986470 | Programmable logic array integrated circuit devices | Richard G. Cliff, Rina Raman, L. Todd Cope, Joseph Huang, Bruce B. Pedersen | 1999-11-16 |
| 5982195 | Programmable logic device architectures | Richard G. Cliff, Francis B. Heile, Joseph Huang, Fung Fung Lee, Cameron McClintock +5 more | 1999-11-09 |
| 5977793 | Programmable logic device with hierarchical interconnection resources | Richard G. Cliff, Christopher F. Lane, Ketan Zaveri, Manuel Mejia, David Jefferson +2 more | 1999-11-02 |
| 5963069 | System for distributing clocks using a delay lock loop in a programmable logic circuit | David Jefferson, L. Todd Cope, Richard G. Cliff | 1999-10-05 |
| 5963049 | Programmable logic array integrated circuit architectures | Richard G. Cliff, Francis B. Heile, Joseph Huang, Christopher F. Lane, Fung Fung Lee +7 more | 1999-10-05 |
| 5942914 | PLD with split multiplexed inputs from global conductors | Christopher F. Lane | 1999-08-24 |
| 5909126 | Programmable logic array integrated circuit devices with interleaved logic array blocks | Richard G. Cliff, Francis B. Heile, Joseph Huang, Christopher F. Lane, Fung Fung Lee +7 more | 1999-06-01 |
| 5894228 | Tristate structures for programmable logic devices | Richard G. Cliff | 1999-04-13 |
| 5883526 | Hierarchical interconnect for programmable logic devices | Manuel Mejia | 1999-03-16 |
| 5850151 | Programmable logic array intergrated circuit devices | Richard G. Cliff, David Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane +7 more | 1998-12-15 |
| 5850152 | Programmable logic array integrated circuit devices | Richard G. Cliff, David Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane +7 more | 1998-12-15 |
| 5847617 | Variable-path-length voltage-controlled oscillator circuit | David Jefferson, Richard G. Cliff, Cameron McClintock | 1998-12-08 |
| 5825197 | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices | Christopher F. Lane, Bonnie I. Wang | 1998-10-20 |
| 5815024 | Look-up table using multi-level decode | Anil Gupta | 1998-09-29 |
| 5764080 | Input/output interface circuitry for programmable logic array integrated circuit devices | Joseph Huang, Richard G. Cliff | 1998-06-09 |
| 5744991 | System for distributing clocks using a delay lock loop in a programmable logic circuit | David Jefferson, L. Todd Cope, Richard G. Cliff | 1998-04-28 |
| 5694058 | Programmable logic array integrated circuits with improved interconnection conductor utilization | Chiakang Sung, Bonnie I. Wang | 1997-12-02 |
| 5689195 | Programmable logic array integrated circuit devices | Richard G. Cliff, Rina Raman, L. Todd Cope, Joseph Huang, Bruce B. Pedersen | 1997-11-18 |
| 5592102 | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices | Christopher F. Lane, Bonnie I. Wang | 1997-01-07 |
| 5543730 | Techniques for programming programmable logic array devices | Richard G. Cliff, Kerry Veenstra, Andreas Papaliolios, Chiakang Sung, Richard Shaw Terrill +2 more | 1996-08-06 |
| 5498975 | Implementation of redundancy on a programmable logic device | Richard G. Cliff, Rina Raman | 1996-03-12 |
| 5485102 | Programmable logic devices with spare circuits for replacement of defects | Richard G. Cliff, Rina Raman | 1996-01-16 |
| 5438295 | Look-up table using multi-level decode | Anil Gupta | 1995-08-01 |
| 5434514 | Programmable logic devices with spare circuits for replacement of defects | Richard G. Cliff, Rina Raman | 1995-07-18 |