Issued Patents All Time
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7042259 | Adaptive frequency clock generation system | Javed S. Barkatullah, Paul D. Madland | 2006-05-09 |
| 7015741 | Adaptive body bias for clock skew compensation | James W. Tschanz, Siva G. Narendra, Javed S. Barkatullah, Vivek K. De | 2006-03-21 |
| 6943605 | Scan cell designs for a double-edge-triggered flip-flop | Paul J. Thadikaran | 2005-09-13 |
| 6922111 | Adaptive frequency clock signal | Javed S. Barkatullah | 2005-07-26 |
| 6922112 | Clock signal generation and distribution via ring oscillators | Javed S. Barkatullah | 2005-07-26 |
| 6882238 | Method and apparatus for detecting on-die voltage variations | Javed S. Barkatullah | 2005-04-19 |
| 6704892 | Automated clock alignment for testing processors in a bypass mode | Javed S. Barkatullah, Tim Frodsham, David O'Brien | 2004-03-09 |
| 6670833 | Multiple VCO phase lock loop architecture | Ian A. Young | 2003-12-30 |
| 6621313 | High frequency system with duty cycle buffer | Jed Griffin | 2003-09-16 |
| 6622255 | Digital clock skew detection and phase alignment | Javed S. Barkatullah | 2003-09-16 |
| 6591319 | Glitch protection and detection for strobed data | Robert Greiner | 2003-07-08 |
| 6505262 | Glitch protection and detection for strobed data | Robert Greiner | 2003-01-07 |
| 6489821 | High frequency system with duty cycle buffer | Jed Griffin | 2002-12-03 |
| 6477674 | Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements | Sarah E. Bates, R. Tim Frodsham, Anne Meixner, David O'Brien, Rajay R. Pai +2 more | 2002-11-05 |
| 6477657 | Circuit for I/O clock generation | R. Tim Frodsham, E. Jeffrey Wight | 2002-11-05 |
| 6469533 | Measuring a characteristic of an integrated circuit | Keng L. Wong, Rachael Parker, Hung-Piao Ma | 2002-10-22 |
| 6469550 | Parallel phase locked loops skew measure and dynamic skew and jitter error compensation method and apparatus | — | 2002-10-22 |
| 6320424 | Method of providing and circuit for providing phase lock loop frequency overshoot control | Yi-Jen Lu, Keng L. Wong | 2001-11-20 |
| 6266779 | Clock enable generation, synchronization, and distribution | — | 2001-07-24 |
| 6169424 | Self-biasing sense amplifier | — | 2001-01-02 |
| 6043717 | Signal synchronization and frequency synthesis system configurable as PLL or DLL | — | 2000-03-28 |