Issued Patents All Time
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10020931 | Apparatus for dynamically adapting a clock generator with respect to changes in power supply | Mohamed A. Abdelmoneum, Amr M. Lotfy, Mamdouh O. Abd El-Mejeed, Mohamed A. Abdelsalam | 2018-07-10 |
| 9876491 | Apparatus, system, and method for re-synthesizing a clock signal | Mark L. Neidengard, Vaughn J. Grossnickle, Jeffrey Krieger | 2018-01-23 |
| 9836078 | Clock generation system with dynamic distribution bypass mode | Allan Feldman, Mark L. Neidengard, Vaughn J. Grossnickle, Praveen Mosalikanti | 2017-12-05 |
| 9628094 | Apparatus and method for fast phase locking for digital phase locked loop | Amr M. Lotfy, Mohamed A. Abdelsalam, Mamdouh O. Abd El-Mejeed, Mohamed A. Abdelmoneum, Mark Elzinga +3 more | 2017-04-18 |
| 9450589 | Clock generation system with dynamic distribution bypass mode | Allan Feldman, Mark L. Neidengard, Vaughn J. Grossnickle, Praveen Mosalikanti | 2016-09-20 |
| 9257994 | Apparatus and system for digitally controlled oscillator | Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Mohamed A. Abdelmoneum | 2016-02-09 |
| 9190991 | Apparatus, system, and method for re-synthesizing a clock signal | Mark L. Neidengard, Vaughn J. Grossnickle, Jeffrey Krieger | 2015-11-17 |
| 8878579 | System and method for scaling power of a phase-locked loop architecture | Vaughn J. Grossnickle | 2014-11-04 |
| 8756451 | Frequency synthesis methods and systems | Mark L. Neidengard, Robert Greiner, Vaughn J. Grossnickle | 2014-06-17 |
| 8736328 | Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces | Thomas P. Thomas | 2014-05-27 |
| 8552781 | Digital quadrature phase correction | Praveen Mosalikanti | 2013-10-08 |
| 8502612 | Method and apparatus for determining within-die and across-die variation of analog circuits | Praveen Mosalikanti, Timothy M. Wilson | 2013-08-06 |
| 8350610 | Method and apparatus for fast wake-up of analog biases | Praveen Mosalikanti, Harishankar Sridharan, Jacob Schneider, Pushkar Gorur | 2013-01-08 |
| 8258837 | Controlled clock phase generation | Praveen Mosalikanti | 2012-09-04 |
| 8248124 | Methods and apparatuses for delay-locked loops and phase-locked loops | Praveen Mosalikanti, Christopher P. Mozak | 2012-08-21 |
| 8031017 | Method and apparatus for determining within-die and across-die variation of analog circuits | Praveen Mosalikanti, Timothy M. Wilson | 2011-10-04 |
| 7873134 | Clock generation system | Ravindra B. Venigalla | 2011-01-18 |
| 7724078 | Adjusting PLL/analog supply to track CPU core supply through a voltage regulator | Chaodan Deng, Thomas P. Thomas | 2010-05-25 |
| 7688150 | PLL with controllable bias level | Ravindra B. Venigalla | 2010-03-30 |
| 7562316 | Apparatus for power consumption reduction | James W. Tschanz, Javed S. Barkatullah, Vivek K. De | 2009-07-14 |
| 7342426 | PLL with controlled VCO bias | Javed S. Barkatullah | 2008-03-11 |
| 7282966 | Frequency management apparatus, systems, and methods | Siva G. Narendra, James W. Tschanz, Vivek K. De, Javed S. Barkatullah | 2007-10-16 |
| 7133751 | Method and apparatus for detecting on-die voltage variations | Javed S. Barkatullah | 2006-11-07 |
| 7102402 | Circuit to manage and lower clock inaccuracies of integrated circuits | Javed S. Barkatullah, Charles E. Dike | 2006-09-05 |
| 7096433 | Method for power consumption reduction | James W. Tschanz, Javed S. Barkatullah, Vivek K. De | 2006-08-22 |