Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6772352 | Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve | James M. Dodd | 2004-08-03 |
| 6701819 | Apparatus for launching an object in a fluid environment | Paul E. Moody | 2004-03-09 |
| 6618791 | System and method for controlling power states of a memory device via detection of a chip select signal | James M. Dodd | 2003-09-09 |
| 6604179 | Reading a FIFO in dual clock domains | Andrew M. Volk | 2003-08-05 |
| 6553449 | System and method for providing concurrent row and column commands | James M. Dodd | 2003-04-22 |
| 6553450 | Buffer to multiply memory interface | Jim M. Dodd, John B. Halbert, Randy M. Bonella, Chung Lam | 2003-04-22 |
| 6530006 | System and method for providing reliable transmission in a buffered memory system | James M. Dodd, John B. Halbert, Randy M. Bonella | 2003-03-04 |
| 6519554 | Computer implemented system and method for evaluating gas generator launchers | Thomas J. Gieseke, Jeffrey L. Cipolla | 2003-02-11 |
| 6507530 | Weighted throttling mechanism with rank based throttling for a memory system | James M. Dodd, Lloyd L. Pollard, II, Nitin B. Gupte | 2003-01-14 |
| 6463001 | Circuit and method for merging refresh and access operations for a memory device | — | 2002-10-08 |
| 6449213 | Memory interface having source-synchronous command/address signaling | James M. Dodd, John B. Halbert, Randy M. Bonella | 2002-09-10 |
| 6400631 | Circuit, system and method for executing a refresh in an active memory bank | Jim M. Dodd | 2002-06-04 |
| 6385094 | Method and apparatus for achieving efficient memory subsystem write-to-read turnaround through read posting | — | 2002-05-07 |
| 6370624 | Configurable page closing method and apparatus for multi-port host bridges | Jasmin Ajanovic, Robert N. Murdoch | 2002-04-09 |
| 6336641 | Break-away muzzle cap retention mechanism | — | 2002-01-08 |
| 6252821 | Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices | Puthiya K. Nizar | 2001-06-26 |
| 6226730 | Achieving page hit memory cycles on a virtual address reference | Robert N. Murdoch | 2001-05-01 |
| 6212611 | Method and apparatus for providing a pipelined memory controller | Puthiya K. Nizar | 2001-04-03 |
| 6199151 | Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle | Mikal C. Hunsaker, Robert N. Murdoch | 2001-03-06 |
| 6199145 | Configurable page closing method and apparatus for multi-port host bridges | Jasmin Ajanovic, Robert N. Murdoch | 2001-03-06 |
| 6154825 | Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations | Robert N. Murdoch, Kuljit S. Bains, Narendra S. Khandekar | 2000-11-28 |
| 6128749 | Cross-clock domain data transfer method and apparatus | David J. McDonnell, Andrew M. Volk | 2000-10-03 |
| 6112306 | Self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state | Andrew M. Volk | 2000-08-29 |
| 6038673 | Computer system with power management scheme for DRAM devices | Samuel Benn | 2000-03-14 |
| 5908982 | Test apparatus for rotary drive | James B. Walsh | 1999-06-01 |