Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7171347 | Logic verification in large systems | Manpreet S. Khaira, Steve W. Otto, Honghua Yang, Jeremy S. Casas, Erik M. Seligman | 2007-01-30 |
| 6198684 | Word line decoder for dual-port cache memory | Kevin X. Zhang, Thomas D. Fletcher | 2001-03-06 |
| 6006299 | Apparatus and method for caching lock conditions in a multi-processor system | Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Nitin V. Sarangdhar, Matthew A. Fisch | 1999-12-21 |
| 5715428 | Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system | Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Michael W. Rhodehamel, Nitin V. Sarangdhar +2 more | 1998-02-03 |
| 5680572 | Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers | Haitham Akkary, Jeffrey M. Abramson, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +2 more | 1997-10-21 |
| 5671444 | Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers | Haitham Akkary, Jeffrey M. Abramson, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +2 more | 1997-09-23 |
| 5630075 | Write combining buffer for sequentially addressed partial line operations originating from a single instruction | Andrew F. Glew, Nitin V. Sarangdhar | 1997-05-13 |
| 5561780 | Method and apparatus for combining uncacheable write data into cache-line-sized write buffers | Andy Glew, Nitin V. Sarangdhar | 1996-10-01 |
| 5526510 | Method and apparatus for implementing a single clock cycle line replacement in a data cache unit | Haitham Akkary, Rob MURRAY, Brent E. Lince, Paul D. Madland, Andrew F. Glew +1 more | 1996-06-11 |