Issued Patents All Time
Showing 51–75 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8933953 | Managing active thread dependencies in graphics processing | James M. Holland, Prasoonkumar Surti | 2015-01-13 |
| 8914800 | Behavioral model based multi-threaded architecture | Thomas A. Piazza | 2014-12-16 |
| 8914618 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Richard Hankins, Per Hammarlund, Dion Rodgers +8 more | 2014-12-16 |
| 8843913 | Dynamic linking and loading of post-processing kernels | Guei-Yuan Lueh, Xiaoying He, Xuefeng Zhang, Yuenian Yang, Ping-Chen Liu +1 more | 2014-09-23 |
| 8804757 | Configurable motion estimation | Ning Lu, Satyaki Koneru | 2014-08-12 |
| 8799876 | Method and apparatus for assigning subroutines | Guei-Yuan Lueh, Andrew T. Riffel, Bixia Zheng, Lian Tang | 2014-08-05 |
| 8544019 | Thread queueing method and apparatus | Thomas A. Piazza, Brian D. Rauchfuss, Sreedevi Chalasani, Steven J. Spangler | 2013-09-24 |
| 8522242 | Conditional batch buffer execution | Wishwesh Anil Gandhi | 2013-08-27 |
| 8484391 | Configurable buffer allocation for multi-format video processing | Hiu-Fai R. Chan, Scott W. Cheng | 2013-07-09 |
| 8446961 | Color gamut scalability techniques | Yi-Jen Chiu, Lidong Xu, Ya-Ti Peng | 2013-05-21 |
| 8448179 | Processing architecture having passive threads and active semaphores | Thomas A. Piazza | 2013-05-21 |
| 8295357 | Method and apparatus for angular-directed spatial deinterlacer | Yi-Jen Chiu, Sang-Hee Lee | 2012-10-23 |
| 8280936 | Packed restricted floating point representation and logic for conversion to single precision float | — | 2012-10-02 |
| 8271986 | Visual and graphical data processing using a multi-threaded architecture | Thomas A. Piazza | 2012-09-18 |
| 8208560 | Bit depth enhancement for scalable video coding | Yi-Jen Chiu, Yingta Yeh | 2012-06-26 |
| 8203557 | System co-processor | Katen Shah | 2012-06-19 |
| 8166320 | Power aware software pipelining for hardware accelerators | Ron Gabor, Alon Naveh, Doron Rajwan, James Varga, Gady Yearim +1 more | 2012-04-24 |
| 7975272 | Thread queuing method and apparatus | Thomas A. Piazza, Brian D. Rauchfuss, Sreedevi Chalasani, Steven J. Spangler | 2011-07-05 |
| 7941791 | Programming environment for heterogeneous processor resource integration | Perry Wang, Jamison D. Collins, Gautham Chinya, Hong Wang, Xinmin Tian +1 more | 2011-05-10 |
| 7907138 | System co-processor | Katen Shah | 2011-03-15 |
| 7904907 | Processing architecture having passive threads and active semaphores | Thomas A. Piazza | 2011-03-08 |
| 7861249 | Thread to thread communication | Michael K. Dwyer | 2010-12-28 |
| 7830397 | Rendering multiple clear rectangles using a pre-rendered depth buffer | Prasoonkumar Surti, Steven J. Spangler | 2010-11-09 |
| 7725745 | Power aware software pipelining for hardware accelerators | Ron Gabor, Alon Naveh, Doron Rajwan, James Varga, Gady Yearim +1 more | 2010-05-25 |
| 7688232 | Optimal selection of compression entries for compressing program instructions | Chu-Cheow Lim, Guei-Yuan Lueh, Bixia Zheng | 2010-03-30 |