Issued Patents All Time
Showing 26–50 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11243768 | Mechanism for saving and retrieving micro-architecture context | Efraim Rotem, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen | 2022-02-08 |
| 11221857 | Collaborative processor and system performance and power management | Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall +2 more | 2022-01-11 |
| 11216276 | Controlling power state demotion in a processor | Hisham Abu-Salah, Daniel D. Lederman, Nir Rosenzweig, Efraim Rotem, Esfir Natanzon +2 more | 2022-01-04 |
| 11182315 | Apparatuses, methods, and systems for hardware control of processor performance levels | Efraim Rotem, Doron Rajwan, Hisham Abu Salah, Ariel Gur, Guy M. Therien +1 more | 2021-11-23 |
| 11157329 | Technology for managing per-core performance states | Hisham Abu-Salah, Nir Rosenzweig, Efraim Rotem | 2021-10-26 |
| 11093278 | Modifying processor frequency based on interrupt rate | Michael W. Chynoweth, Rajshree Chabukswar, Jeremy J. Shrall | 2021-08-17 |
| 11074191 | Linear to physical address translation with support for page attributes | Ben-Zion Friedman, Jacob Doweck, James B. Crossland, Ohad Falik | 2021-07-27 |
| 11029744 | System, apparatus and method for controlling a processor based on effective stress information | Efraim Rotem, Esfir Natanzon, Doron Rajwan, Dorit Shapira, Lily P. Looi +2 more | 2021-06-08 |
| 10990154 | System, apparatus and method for loose lock-step redundancy power management | Efraim Rotem, Doron Rajwan, Nir Rosenzweig, Yoni Aizik | 2021-04-27 |
| 10990155 | System, apparatus and method for loose lock-step redundancy power management | Efraim Rotem, Doron Rajwan, Nir Rosenzweig, Yoni Aizik | 2021-04-27 |
| 10990395 | System and method for communication using a register management array circuit | Alexander Gendler, Michael Mishaeli | 2021-04-27 |
| 10990161 | Processor having accelerated user responsiveness in constrained environment | Efraim Rotem, Doron Rajwan, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos +1 more | 2021-04-27 |
| 10963034 | System, apparatus and method for loose lock-step redundancy power management in a processor | Efraim Rotem, Doron Rajwan, Nir Rosenzweig, Yoni Aizik | 2021-03-30 |
| 10955899 | System, apparatus and method for responsive autonomous hardware performance state control of a processor | Hisham Abu Salah, Efraim Rotem, Yoni Aizik, Daniel D. Lederman | 2021-03-23 |
| 10884483 | Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency | Jawad Haj-Yihia, Vijay S. R. Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko +2 more | 2021-01-05 |
| 10705588 | Enabling a non-core domain to control memory bandwidth in a processor | Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Ryan D. Wells | 2020-07-07 |
| 10678319 | Multi-level loops for computer processor control | Doron Rajwan, Efraim Rotem, Avinash N. Ananthakrishnan, Dorit Shapira | 2020-06-09 |
| 10620682 | System, apparatus and method for processor-external override of hardware performance state control of a processor | Nikhil Gupta, Israel Hirsh, Esfir Natanzon, Nir Rosenzweig, Efraim Rotem +2 more | 2020-04-14 |
| 10613614 | Dynamically controlling cache size to maximize energy efficiency | Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more | 2020-04-07 |
| 10564699 | Dynamically controlling cache size to maximize energy efficiency | Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more | 2020-02-18 |
| 10558490 | Mechanism for issuing requests to an accelerator from multiple threads | Ronny Ronen, Boris Ginzburg | 2020-02-11 |
| 10545793 | Thread scheduling using processing engine information | Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov +6 more | 2020-01-28 |
| 10503509 | System and method for communication using a register management array circuit | Alexander Gendler, Michael Mishaeli | 2019-12-10 |
| 10503517 | Method for booting a heterogeneous system and presenting a symmetric core view | Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt +19 more | 2019-12-10 |
| 10503550 | Dynamic performance biasing in a processor | Monica Gupta, Russell J. Fenger, Vijay Dhanraj, Deepak Samuel Kirubakaran, Srividya Ambale +2 more | 2019-12-10 |