Issued Patents All Time
Showing 101–125 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9921807 | Floating point scaling processors, methods, systems, and instructions | Cristina S. Anderson, Robert Valentine, Simon Rubanovich, Benny Eitan | 2018-03-20 |
| 9904547 | Packed data rearrangement control indexes generation processors, methods, systems and instructions | Elmoustapha Ould-Ahmed-Vall, Seth Abraham, Robert Valentine, Zeev Sperber | 2018-02-27 |
| 9898283 | Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset | Seth Abraham, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Zeev Sperber | 2018-02-20 |
| 9864602 | Packed rotate processors, methods, systems, and instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal San Andrian, Suleyman Sair, Bret L. Toll +2 more | 2018-01-09 |
| 9678751 | Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction | Elmoustapha Ould-Ahmed-Vall, Moustapha Hagog, Robert Valentine, Simon Rubanovich, Zeev Sperber +2 more | 2017-06-13 |
| 9658850 | Apparatus and method of improved permute instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2017-05-23 |
| 9639354 | Packed data rearrangement control indexes precursors generation processors, methods, systems, and instructions | Seth Abraham, Robert Valentine, Elmoustapha Ould-Ahmed-Vall, Zeev Sperber | 2017-05-02 |
| 9619236 | Apparatus and method of improved insert instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2017-04-11 |
| 9619226 | Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction | Mostafa Hagog, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Simon Rubanovich, Zeev Sperber | 2017-04-11 |
| 9606770 | Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions | Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Benny Eitan | 2017-03-28 |
| 9588764 | Apparatus and method of improved extract instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2017-03-07 |
| 9582464 | Systems, apparatuses, and methods for performing a double blocked sum of absolute differences | Elmoustapha Ould-Ahmed-Vall, Mostafa Hagog, Robert Valentine, Simon Rubanovich, Zeev Sperber | 2017-02-28 |
| 9542154 | Fused multiply add operations using bit masks | Simon Rubanovich, Thierry Pons, Zeev Sperber | 2017-01-10 |
| 9513918 | Apparatus and method for performing permute operations | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mostafa Hagog, Jesus Corbal, Bret L. Toll +3 more | 2016-12-06 |
| 9513871 | Floating point round-off amount determination processors, methods, systems, and instructions | Cristina S. Anderson, Bret L. Toll, Robert Valentine, Simon Rubanovich | 2016-12-06 |
| 9495162 | Apparatus and method for performing a permute operation | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mostafa Hagog, Jesus Corbal, Tal Uliel +1 more | 2016-11-15 |
| 9465580 | Math circuit for estimating a transcendental function | Jose-Alejandro Pineiro, Simon Rubanovich, Benny Eitan, Thomas D. Fletcher | 2016-10-11 |
| 9459865 | Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction | Elmoustapha Ould-Ahmed-Vall, Mostafa Hagog, Robert Valentine, Simon Rubanovich, Zeev Sperber | 2016-10-04 |
| 9448765 | Floating point scaling processors, methods, systems, and instructions | Christina Anderson, Robert Valentine, Simon Rubanovich, Benny Eitan | 2016-09-20 |
| 9274752 | Leading change anticipator logic | Simon Rubanovich, Thierry Pons, Zeev Sperber | 2016-03-01 |
| 9092226 | Efficient parallel floating point exception handling in a processor | Zeev Sperber, Shachar Finkelstein, Gregory Pribush, Guy Bale, Thierry Pons | 2015-07-28 |
| 8914430 | Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions | Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Benny Eitan | 2014-12-16 |
| 8706789 | Performing reciprocal instructions with high accuracy | Zeev Sperber, Cristina S. Anderson, Benny Eitan, Simon Rubanovich | 2014-04-22 |
| 8600049 | Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation | Shay Gueron, Zeev Sperber | 2013-12-03 |
| 8194854 | Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation | Shay Gueron, Zeev Sperber | 2012-06-05 |